WIP lmar cleanups and improvements

[citrus-it]

No description provided.

[tomsteininger]

testing this code on mb-2 (2YFH3T3G), also with N1-N5: FW_REV=RH110013, and N6-N9: FW_REV=RH110017.
just a note that at commit time, assuming lmar Cargo.toml will bump rev to 0.3.6, so my comments are using that designator for this state of code.

[tomsteininger]

from lmar 0.3.4 , there is an improvement that apparently fixes the NaN issue:

0.3.4 results: (shows error on this port)

2YFH3T3G # ../../lmar 60/1/2 downstream -l all -v
lmar: margining lanes: [Lane(0), Lane(1), Lane(2), Lane(3)]
lmar: margin duration 1s
lmar: ReportCapabilities {
    independent_error_sampler: false,
    sample_reporting_method: Count,
    independent_left_right_sampling: true,
    independent_up_down_voltage: true,
    voltage_supported: true,
}
lmar: MarginingLimits {
    num_voltage_steps: Some(
        29,
    ),
    num_timing_steps: 16,
    max_timing_offset: 25,
    max_voltage_offset: Some(
        13,
    ),
    sampling_rate_voltage: Some(
        63,
    ),
    sampling_rate_timing: 63,
}
lmar: saving lane 0 to "margin-1987-01-04T00-20-57/margin-results-b60-d1-f2-l0"
lmar: saving lane 1 to "margin-1987-01-04T00-20-57/margin-results-b60-d1-f2-l1"
lmar: saving lane 2 to "margin-1987-01-04T00-20-57/margin-results-b60-d1-f2-l2"
lmar: saving lane 3 to "margin-1987-01-04T00-20-57/margin-results-b60-d1-f2-l3"
lmar: lane 0 (time)     : ████████████████████ 32 / 32
lmar: lane 0 (voltage)  : ████████████████████ 58 / 58
lmar: lane 1 (time)     : ████████████████████ 32 / 32
lmar: lane 1 (voltage)  : ████████████████████ 58 / 58
lmar: lane 2 (time)     : ████████████████████ 32 / 32
lmar: lane 2 (voltage)  : ████████████████████ 58 / 58
lmar: lane 3 (time)     : ████████████████████ 32 / 32
lmar: lane 3 (voltage)  : ████████████████████ 58 / 58                                                                                       lmar: margining lane 0 failed: Failed to margin point: StepUpDown { direction: Some(Down), steps: Steps(27) }: An error occurred during lane margining: Failed to finish margin setup within 2s (polls=994, last_error_count=Some(ErrorCount(0)), cmd=StepUpDown(StepUpDown { direction: Some(Down), steps: Steps(27) }))

this version ... no error.

2YFH3T3G # ../lmar.0.3.6 60/1/2 downstream -l all -v
lmar: margining lanes: [Lane(0), Lane(1), Lane(2), Lane(3)]
lmar: margin duration 1s
lmar: ReportCapabilities {
    independent_error_sampler: false,
    sample_reporting_method: Count,
    independent_left_right_sampling: true,
    independent_up_down_voltage: true,
    voltage_supported: true,
}
lmar: MarginingLimits {
    num_voltage_steps: Some(
        29,
    ),
    num_timing_steps: 16,
    max_timing_offset: 25,
    max_voltage_offset: Some(
        13,
    ),
    sampling_rate_voltage: Some(
        63,
    ),
    sampling_rate_timing: 63,
}
Timing: steps=16 offset=25 step=1.5625%
Voltage: steps=29 offset=13 step=0.004482758620689655V
lmar: saving lane 0 to "margin-1987-01-04T00-10-22/margin-results-b60-d1-f2-l0"
lmar: saving lane 1 to "margin-1987-01-04T00-10-22/margin-results-b60-d1-f2-l1"
lmar: saving lane 2 to "margin-1987-01-04T00-10-22/margin-results-b60-d1-f2-l2"
lmar: saving lane 3 to "margin-1987-01-04T00-10-22/margin-results-b60-d1-f2-l3"
lmar: lane 0 (time)     : ████████████████████ 32 / 32
lmar: lane 0 (voltage)  : ████████████████████ 58 / 58
lmar: lane 1 (time)     : ████████████████████ 32 / 32
lmar: lane 1 (voltage)  : ████████████████████ 58 / 58
lmar: lane 2 (time)     : ████████████████████ 32 / 32
lmar: lane 2 (voltage)  : ████████████████████ 58 / 58
lmar: lane 3 (time)     : ████████████████████ 32 / 32
lmar: lane 3 (voltage)  : ████████████████████ 58 / 58 

continuing testing.

I do NOT think the parallel vs. serial is the primary fix here, so I'd like to try a version of this code with parallel scan (ignoring the IndErrorSampler=0 warning).