CL/aarch64: implement the wasm SIMD pseudo-max/min and FP-rounding in…#2312
Merged
julian-seward1 merged 1 commit intobytecodealliance:mainfrom Oct 26, 2020
Merged
Conversation
github-actions
bot
added
cranelift
yurydelendik
approved these changes
Oct 23, 2020
Contributor
yurydelendik
left a comment
yurydelendik
left a comment
There was a problem hiding this comment.
Looks good with better fmin_pseudo/ fmax_pseudo instruction descriptions (maybe even a note at lower_inst.rs implementation?)
julian-seward1
force-pushed
the
arm64-simd-pminmax-round
branch
3 times, most recently
from
df58133 to
bfceb8c
Compare
…structions This patch implements, for aarch64, the following wasm SIMD extensions Floating-point rounding instructions WebAssembly/simd#232 Pseudo-Minimum and Pseudo-Maximum instructions WebAssembly/simd#122 The changes are straightforward: * `build.rs`: the relevant tests have been enabled * `cranelift/codegen/meta/src/shared/instructions.rs`: new CLIF instructions `fmin_pseudo` and `fmax_pseudo`. The wasm rounding instructions do not need any new CLIF instructions. * `cranelift/wasm/src/code_translator.rs`: translation into CLIF; this is pretty much the same as any other unary or binary vector instruction (for the rounding and the pmin/max respectively) * `cranelift/codegen/src/isa/aarch64/lower_inst.rs`: - `fmin_pseudo` and `fmax_pseudo` are converted into a two instruction sequence, `fcmpgt` followed by `bsl` - the CLIF rounding instructions are converted to a suitable vector `frint{n,z,p,m}` instruction. * `cranelift/codegen/src/isa/aarch64/inst/mod.rs`: minor extension of `pub enum VecMisc2` to handle the rounding operations. And corresponding `emit` cases.
julian-seward1
force-pushed
the
arm64-simd-pminmax-round
branch
from
bfceb8c to
e20f0cf
Compare
bjorn3
added a commit
to bjorn3/wasmtime
that referenced
this pull request
Jul 27, 2021
It was added in bytecodealliance#2312
bjorn3
added a commit
to bjorn3/wasmtime
that referenced
this pull request
Aug 27, 2021
It was added in bytecodealliance#2312
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
…structions
This patch implements, for aarch64, the following wasm SIMD extensions
Floating-point rounding instructions
WebAssembly/simd#232
Pseudo-Minimum and Pseudo-Maximum instructions
WebAssembly/simd#122
The changes are straightforward:
build.rs: the relevant tests have been enabledcranelift/codegen/meta/src/shared/instructions.rs: new CLIF instructionsfmin_pseudoandfmax_pseudo. The wasm rounding instructions do not needany new CLIF instructions.
cranelift/wasm/src/code_translator.rs: translation into CLIF; this ispretty much the same as any other unary or binary vector instruction (for
the rounding and the pmin/max respectively)
cranelift/codegen/src/isa/aarch64/lower_inst.rs:fmin_pseudoandfmax_pseudoare converted into a two instructionsequence,
fcmpgtfollowed bybslfrint{n,z,p,m}instruction.cranelift/codegen/src/isa/aarch64/inst/mod.rs: minor extension ofpub enum VecMisc2to handle the rounding operations. And correspondingemitcases.