Feature/pcie#39

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parhamsoltani wants to merge 10 commits intoVHDL:releasefrom

parhamsoltani:feature/pcie

Commits on Jul 9, 2025

v1.0.0
Paebbels
authored

Commits on Jul 27, 2025

Commits on Dec 7, 2025

v1.0.1
Paebbels
authored

Commits on Dec 10, 2025

Refactor Wishbone and Avalon interfaces to use spec-compliant signal names with VHDL-2019 bit types
parhamsoltani
committed
minor change on compileorder
parhamsoltani
committed

Commits on Dec 11, 2025

updated wishbone using std_ulogic/std_ulogic_vector, and unsigned types with UpperCamelCase naming
parhamsoltani
committed
Revert "updated wishbone using std_ulogic/std_ulogic_vector, and unsigned types with UpperCamelCase naming"
parhamsoltani
committed
This reverts commit d05a9dfa1dbeca6c137467a2c9827fd5d0d6045a.
parhamsoltani
committed

Commits on Jan 6, 2026

Add PCI Express (PCIe) 4.0 interface support
parhamsoltani
committed