UART_TX-RX is an open-source, synthesizable Universal Asynchronous Receiver–Transmitter (UART) core written in Verilog HDL.
UART (Universal Asynchronous Receiver–Transmitter) is a widely used serial communication protocol in embedded systems and SoCs. This project provides a modular UART implementation consisting of:
- UART Transmitter (TX)
- UART Receiver (RX)
- Configurable baud rate generator
- Optional FIFO buffering
- Top-level integration module
- Verification-ready testbenches
- Fully synthesizable Verilog RTL
- Separate TX and RX modules
- Configurable baud rate
- FIFO-based buffering support
- Clean and modular RTL structure
- Loopback and directed testbenches
- Simulation automation scripts
- FPGA-ready constraint support
- Beginner-friendly and extensible
MIT LICENSE See the LICENSE file for details.
Maintainer Arjun P Shetty Open to collaboration, mentorship, and community contributions.
Detailed design and verification documents are available in the docs/ directory.
Please read CONTRIBUTING.md before submitting changes.
See SECURITY.md for responsible disclosure.
git clone https://github.com/ArjunPShetty/UART_TX-RX.git
cd UART_TX-RX