From 1c46415e354e9c68742acd94b188e4a24cab7147 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 27 Jul 2025 17:35:33 +0200 Subject: [PATCH 1/8] Added OSVVM build file. --- build.pro | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 build.pro diff --git a/build.pro b/build.pro new file mode 100644 index 0000000..5cd91d5 --- /dev/null +++ b/build.pro @@ -0,0 +1,54 @@ +# ==================================================================================================================== # +# Copyright 2016-2025 Open Source VHDL Group # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# ==================================================================================================================== # +# VHDLRevision: VHDL-2019 +# VHDLLibrary: Interfaces + +library Interfaces + +# Common definitions +analyze IO/Common.vhdl + +# Internal bus structures +analyze AMBA/AXI/v4/AXI4Common.vhdl +analyze AMBA/AXI/v4/AXI4.vhdl +analyze AMBA/AXI/v4/AXI4_Generic.vhdl + +analyze AMBA/AXI/v4/AXI4Lite.vhdl +analyze AMBA/AXI/v4/AXI4Lite_Generic.vhdl +analyze AMBA/AXI/v4/AXI4Lite.presized.vhdl + +analyze AMBA/AXI/v4/AXI4Stream.vhdl +analyze AMBA/AXI/v4/AXI4Stream_Generic.vhdl + +# Low-speed interfaces +analyze IO/I2C.vhdl +analyze IO/SPI.vhdl +analyze IO/I2S.vhdl +analyze IO/JTAG.vhdl +analyze IO/UART.vhdl + +# Ethernet +analyze IO/Ethernet.vhdl +analyze IO/Cages.vhdl + +# Video interfaces +analyze Video/VGA.vhdl +analyze MIPI/C-PHY.vhdl +analyze MIPI/D-PHY.vhdl +analyze MIPI/M-PHY.vhdl + +# Miscellaneous interfaces +analyze PoC/CSE.vhdl From 86d0983381af5d7ff6a96bb0636280596fc347e7 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 27 Jul 2025 17:36:30 +0200 Subject: [PATCH 2/8] Axi4: Moved STROBE_BITS from package generics to computed package constant. --- AMBA/AXI/v4/AXI4.vhdl | 4 ++-- AMBA/AXI/v4/AXI4_Generic.vhdl | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/AMBA/AXI/v4/AXI4.vhdl b/AMBA/AXI/v4/AXI4.vhdl index 0f887c2..8b521f4 100644 --- a/AMBA/AXI/v4/AXI4.vhdl +++ b/AMBA/AXI/v4/AXI4.vhdl @@ -85,8 +85,8 @@ package Axi4 is type Axi4_ReadData_Interface is record -- Handshake signals - Valid : std_ulogic; - Ready : std_ulogic; + Valid : std_ulogic; + Ready : std_ulogic; -- Payload signals ID : ID_Type; diff --git a/AMBA/AXI/v4/AXI4_Generic.vhdl b/AMBA/AXI/v4/AXI4_Generic.vhdl index d03b4c8..8b4689f 100644 --- a/AMBA/AXI/v4/AXI4_Generic.vhdl +++ b/AMBA/AXI/v4/AXI4_Generic.vhdl @@ -32,11 +32,12 @@ package Axi4_Generic is generic ( constant ADDRESS_BITS : positive; constant DATA_BITS : positive; - constant STROBE_BITS : positive := DATA_BITS / 8; constant ID_BITS : positive; constant USER_BITS : positive ); + constant STROBE_BITS : positive := DATA_BITS / 8; + subtype Axi4_Address_SizedInterface is Axi4_Address_Interface( ID(ID_BITS - 1 downto 0), Address(ADDRESS_BITS - 1 downto 0), @@ -86,7 +87,7 @@ package Axi4_Generic is User(USER_BITS - 1 downto 0) ) ); - + subtype Axi4_SizedInterface_Vector is Axi4_Interface_Vector(open)( WriteAddress( ID(ID_BITS - 1 downto 0), From d05a9dfa1dbeca6c137467a2c9827fd5d0d6045a Mon Sep 17 00:00:00 2001 From: parhamsoltani Date: Thu, 11 Dec 2025 01:07:42 +0330 Subject: [PATCH 3/8] Refactor Wishbone and Avalon interfaces to use spec-compliant signal names with VHDL-2019 bit types --- Avalon/v1/AvalonCommon.vhdl | 47 +++++++++++ Avalon/v1/AvalonMM.vhdl | 111 ++++++++++++++++++++++++++ Avalon/v1/AvalonMM_Generic.vhdl | 71 +++++++++++++++++ Avalon/v1/AvalonST.vhdl | 91 ++++++++++++++++++++++ Avalon/v1/AvalonST_Generic.vhdl | 62 +++++++++++++++ Wishbone/vB3/Wishbone.vhdl | 121 +++++++++++++++++++++++++++++ Wishbone/vB3/WishboneCommon.vhdl | 57 ++++++++++++++ Wishbone/vB3/Wishbone_Generic.vhdl | 79 +++++++++++++++++++ build.pro | 10 +++ compileorder.list | 11 +++ 10 files changed, 660 insertions(+) create mode 100644 Avalon/v1/AvalonCommon.vhdl create mode 100644 Avalon/v1/AvalonMM.vhdl create mode 100644 Avalon/v1/AvalonMM_Generic.vhdl create mode 100644 Avalon/v1/AvalonST.vhdl create mode 100644 Avalon/v1/AvalonST_Generic.vhdl create mode 100644 Wishbone/vB3/Wishbone.vhdl create mode 100644 Wishbone/vB3/WishboneCommon.vhdl create mode 100644 Wishbone/vB3/Wishbone_Generic.vhdl diff --git a/Avalon/v1/AvalonCommon.vhdl b/Avalon/v1/AvalonCommon.vhdl new file mode 100644 index 0000000..a58c516 --- /dev/null +++ b/Avalon/v1/AvalonCommon.vhdl @@ -0,0 +1,47 @@ +-- ============================================================================= +-- Authors: +-- Parham Soltani +-- +-- Package: +-- Common types for Avalon Memory-Mapped (MM) interfaces +-- +-- Description: +-- Defines shared types for use in Avalon-MM records +-- +-- License: +-- ============================================================================= +-- Copyright 2016-2025 Open Source VHDL Group +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +package AvalonCommon is + -- Common types (native VHDL-2019 bit types) + subtype Data_Type is bit_vector; + subtype Address_Type is bit_vector; + subtype ByteEnable_Type is bit_vector; + subtype BurstCount_Type is bit_vector; + + -- Avalon-MM Response + subtype Response_Type is bit_vector(1 downto 0); + constant AVALON_RESP_OKAY : Response_Type := "00"; + constant AVALON_RESP_RESERVED : Response_Type := "01"; + constant AVALON_RESP_SLAVEERROR : Response_Type := "10"; + constant AVALON_RESP_DECODEERROR : Response_Type := "11"; + + type Avalon_System_Interface is record + Clk : bit; + Reset : bit; + end record; + +end package; \ No newline at end of file diff --git a/Avalon/v1/AvalonMM.vhdl b/Avalon/v1/AvalonMM.vhdl new file mode 100644 index 0000000..d3e6d40 --- /dev/null +++ b/Avalon/v1/AvalonMM.vhdl @@ -0,0 +1,111 @@ +-- ============================================================================= +-- Authors: +-- Parham Soltani +-- +-- Package: +-- VHDL-2019 Avalon Memory-Mapped (Avalon-MM) interface descriptions +-- +-- Description: +-- Signal names match Avalon specification (address, writedata, readdata, etc.) +-- Uses native VHDL-2019 bit types +-- +-- License: +-- ============================================================================= +-- Copyright 2016-2025 Open Source VHDL Group +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +use work.AvalonCommon.all; + +package AvalonMM is + -- Avalon Memory-Mapped Interface (matching spec signal names) + type AvalonMM_Interface is record + -- Master signals (names match Avalon spec exactly) + address : Address_Type; -- Address + read : bit; -- Read request + write : bit; -- Write request + writedata : Data_Type; -- Write data + byteenable : ByteEnable_Type; -- Byte enable + + -- Slave signals + readdata : Data_Type; -- Read data + readdatavalid : bit; -- Read data valid + waitrequest : bit; -- Wait request + response : Response_Type; -- Response + + -- Optional burst signals + burstcount : BurstCount_Type; -- Burst count + + -- Optional pipelining signals + writeresponsevalid : bit; -- Write response valid + + -- Optional lock signal + lock : bit; -- Lock + + -- Optional debug signals + debugaccess : bit; -- Debug access + end record; + type AvalonMM_Interface_Vector is array(natural range <>) of AvalonMM_Interface; + + -- Master view (from master's perspective) + view AvalonMM_MasterView of AvalonMM_Interface is + -- Master outputs + address : out; + read : out; + write : out; + writedata : out; + byteenable : out; + burstcount : out; + lock : out; + debugaccess : out; + + -- Master inputs (slave outputs) + readdata : in; + readdatavalid : in; + waitrequest : in; + response : in; + writeresponsevalid : in; + end view; + alias AvalonMM_SlaveView is AvalonMM_MasterView'converse; + + -- Simplified interface without optional signals + type AvalonMM_Simple_Interface is record + -- Master signals + address : Address_Type; + read : bit; + write : bit; + writedata : Data_Type; + byteenable : ByteEnable_Type; + + -- Slave signals + readdata : Data_Type; + waitrequest : bit; + end record; + type AvalonMM_Simple_Interface_Vector is array(natural range <>) of AvalonMM_Simple_Interface; + + view AvalonMM_Simple_MasterView of AvalonMM_Simple_Interface is + -- Master outputs + address : out; + read : out; + write : out; + writedata : out; + byteenable : out; + + -- Master inputs + readdata : in; + waitrequest : in; + end view; + alias AvalonMM_Simple_SlaveView is AvalonMM_Simple_MasterView'converse; + +end package; \ No newline at end of file diff --git a/Avalon/v1/AvalonMM_Generic.vhdl b/Avalon/v1/AvalonMM_Generic.vhdl new file mode 100644 index 0000000..aab6ef9 --- /dev/null +++ b/Avalon/v1/AvalonMM_Generic.vhdl @@ -0,0 +1,71 @@ +-- ============================================================================= +-- Authors: +-- Parham Soltani +-- +-- Package: +-- Generic Avalon-MM interface for pre-constraining widths +-- +-- Description: +-- Uses spec-matching names (address, writedata, readdata, byteenable, etc.) +-- +-- License: +-- ============================================================================= +-- Copyright 2016-2025 Open Source VHDL Group +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +use work.AvalonMM.all; + +package AvalonMM_Generic is + generic ( + constant ADDRESS_BITS : positive; + constant DATA_BITS : positive; + constant BURSTCOUNT_BITS : positive := 1 + ); + + constant BYTEENABLE_BITS : positive := DATA_BITS / 8; + + -- Full Avalon-MM interface with all optional signals + subtype AvalonMM_SizedInterface is AvalonMM_Interface( + address(ADDRESS_BITS - 1 downto 0), + writedata(DATA_BITS - 1 downto 0), + readdata(DATA_BITS - 1 downto 0), + byteenable(BYTEENABLE_BITS - 1 downto 0), + burstcount(BURSTCOUNT_BITS - 1 downto 0) + ); + + subtype AvalonMM_SizedInterface_Vector is AvalonMM_Interface_Vector(open)( + address(ADDRESS_BITS - 1 downto 0), + writedata(DATA_BITS - 1 downto 0), + readdata(DATA_BITS - 1 downto 0), + byteenable(BYTEENABLE_BITS - 1 downto 0), + burstcount(BURSTCOUNT_BITS - 1 downto 0) + ); + + -- Simplified Avalon-MM interface + subtype AvalonMM_Simple_SizedInterface is AvalonMM_Simple_Interface( + address(ADDRESS_BITS - 1 downto 0), + writedata(DATA_BITS - 1 downto 0), + readdata(DATA_BITS - 1 downto 0), + byteenable(BYTEENABLE_BITS - 1 downto 0) + ); + + subtype AvalonMM_Simple_SizedInterface_Vector is AvalonMM_Simple_Interface_Vector(open)( + address(ADDRESS_BITS - 1 downto 0), + writedata(DATA_BITS - 1 downto 0), + readdata(DATA_BITS - 1 downto 0), + byteenable(BYTEENABLE_BITS - 1 downto 0) + ); + +end package; \ No newline at end of file diff --git a/Avalon/v1/AvalonST.vhdl b/Avalon/v1/AvalonST.vhdl new file mode 100644 index 0000000..d9791a5 --- /dev/null +++ b/Avalon/v1/AvalonST.vhdl @@ -0,0 +1,91 @@ +-- ============================================================================= +-- Authors: +-- Parham Soltani +-- +-- Package: +-- VHDL-2019 Avalon Streaming (Avalon-ST) interface descriptions +-- +-- Description: +-- Signal names match Avalon-ST specification (data, valid, ready, etc.) +-- Uses native VHDL-2019 bit types +-- +-- License: +-- ============================================================================= +-- Copyright 2016-2025 Open Source VHDL Group +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +use work.AvalonCommon.all; + +package AvalonST is + -- Avalon Streaming Interface (matching spec signal names) + type AvalonST_Interface is record + -- Handshake signals + valid : bit; -- Valid + ready : bit; -- Ready + + -- Payload signals + data : Data_Type; -- Data + + -- Packet signals + startofpacket : bit; -- Start of packet + endofpacket : bit; -- End of packet + empty : bit_vector; -- Empty (number of empty symbols) + + -- Error signal + error : bit_vector; -- Error + + -- Channel signal + channel : bit_vector; -- Channel + end record; + type AvalonST_Interface_Vector is array(natural range <>) of AvalonST_Interface; + + -- Source view (from source's perspective) + view AvalonST_SourceView of AvalonST_Interface is + -- Source outputs + valid : out; + data : out; + startofpacket : out; + endofpacket : out; + empty : out; + error : out; + channel : out; + + -- Source inputs (sink outputs) + ready : in; + end view; + alias AvalonST_SinkView is AvalonST_SourceView'converse; + + -- Simplified interface without optional signals + type AvalonST_Simple_Interface is record + -- Handshake signals + valid : bit; + ready : bit; + + -- Payload signal + data : Data_Type; + end record; + type AvalonST_Simple_Interface_Vector is array(natural range <>) of AvalonST_Simple_Interface; + + view AvalonST_Simple_SourceView of AvalonST_Simple_Interface is + -- Source outputs + valid : out; + data : out; + + -- Source inputs + ready : in; + end view; + alias AvalonST_Simple_SinkView is AvalonST_Simple_SourceView'converse; + +end package; \ No newline at end of file diff --git a/Avalon/v1/AvalonST_Generic.vhdl b/Avalon/v1/AvalonST_Generic.vhdl new file mode 100644 index 0000000..fca699e --- /dev/null +++ b/Avalon/v1/AvalonST_Generic.vhdl @@ -0,0 +1,62 @@ +-- ============================================================================= +-- Authors: +-- Parham Soltani +-- +-- Package: +-- Generic Avalon-ST interface descriptions for pre-constraining +-- +-- Description: +-- Uses spec-matching names (data, valid, ready, channel, etc.) +-- +-- License: +-- ============================================================================= +-- Copyright 2016-2025 Open Source VHDL Group +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +use work.AvalonST.all; + +package AvalonST_Generic is + generic ( + constant DATA_BITS : positive; + constant EMPTY_BITS : positive := 1; + constant ERROR_BITS : positive := 1; + constant CHANNEL_BITS : positive := 1 + ); + + -- Full Avalon-ST interface with all optional signals + subtype AvalonST_SizedInterface is AvalonST_Interface( + data(DATA_BITS - 1 downto 0), + empty(EMPTY_BITS - 1 downto 0), + error(ERROR_BITS - 1 downto 0), + channel(CHANNEL_BITS - 1 downto 0) + ); + + subtype AvalonST_SizedInterface_Vector is AvalonST_Interface_Vector(open)( + data(DATA_BITS - 1 downto 0), + empty(EMPTY_BITS - 1 downto 0), + error(ERROR_BITS - 1 downto 0), + channel(CHANNEL_BITS - 1 downto 0) + ); + + -- Simplified Avalon-ST interface + subtype AvalonST_Simple_SizedInterface is AvalonST_Simple_Interface( + data(DATA_BITS - 1 downto 0) + ); + + subtype AvalonST_Simple_SizedInterface_Vector is AvalonST_Simple_Interface_Vector(open)( + data(DATA_BITS - 1 downto 0) + ); + +end package; \ No newline at end of file diff --git a/Wishbone/vB3/Wishbone.vhdl b/Wishbone/vB3/Wishbone.vhdl new file mode 100644 index 0000000..aa5be8a --- /dev/null +++ b/Wishbone/vB3/Wishbone.vhdl @@ -0,0 +1,121 @@ +-- ============================================================================= +-- Authors: +-- Parham Soltani +-- +-- Package: +-- VHDL-2019 Wishbone interface descriptions +-- +-- Description: +-- Signal names match Wishbone B.4 specification (Cyc, Stb, Ack, Err, etc.) +-- Uses native VHDL-2019 bit types +-- +-- License: +-- ============================================================================= +-- Copyright 2016-2025 Open Source VHDL Group +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +use work.WishboneCommon.all; + +package Wishbone is + -- Classic Wishbone Interface (matching spec signal names) + type Wishbone_Interface is record + -- Master signals (outputs from master perspective) + Cyc : bit; -- CYC_O - Cycle + Stb : bit; -- STB_O - Strobe + We : bit; -- WE_O - Write Enable + Addr : Addr_Type; -- ADR_O - Address + Dat_m : Data_Type; -- DAT_O - Data (Master to Slave) + Sel : Sel_Type; -- SEL_O - Select + + -- Slave signals (outputs from slave perspective) + Ack : bit; -- ACK_I - Acknowledge + Err : bit; -- ERR_I - Error + Rty : bit; -- RTY_I - Retry + Dat_s : Data_Type; -- DAT_I - Data (Slave to Master) + + -- Optional signals for pipelined/burst modes + Cti : Cti_Type; -- CTI_O - Cycle Type Identifier + Bte : Bte_Type; -- BTE_O - Burst Type Extension + + -- Optional tag signals + Tgd_m : Tgd_Type; -- TGD_O - Tag Data (Master) + Tgd_s : Tgd_Type; -- TGD_I - Tag Data (Slave) + Tga : Tga_Type; -- TGA_O - Tag Address + Tgc : Tgc_Type; -- TGC_O - Tag Cycle + + -- Optional signals + Lock : bit; -- LOCK_O - Lock + Stall : bit; -- STALL_I - Pipeline stall + end record; + type Wishbone_Interface_Vector is array(natural range <>) of Wishbone_Interface; + + -- Master view (from master's perspective) + view Wishbone_MasterView of Wishbone_Interface is + -- Master outputs + Cyc : out; + Stb : out; + We : out; + Addr : out; + Dat_m : out; + Sel : out; + Cti : out; + Bte : out; + Tgd_m : out; + Tga : out; + Tgc : out; + Lock : out; + + -- Master inputs (slave outputs) + Ack : in; + Err : in; + Rty : in; + Dat_s : in; + Tgd_s : in; + Stall : in; + end view; + alias Wishbone_SlaveView is Wishbone_MasterView'converse; + + -- Simplified interface without optional signals + type Wishbone_Simple_Interface is record + -- Master signals + Cyc : bit; + Stb : bit; + We : bit; + Addr : Addr_Type; + Dat_m : Data_Type; + Sel : Sel_Type; + + -- Slave signals + Ack : bit; + Dat_s : Data_Type; + end record; + type Wishbone_Simple_Interface_Vector is array(natural range <>) of Wishbone_Simple_Interface; + + view Wishbone_Simple_MasterView of Wishbone_Simple_Interface is + -- Master outputs + Cyc : out; + Stb : out; + We : out; + Addr : out; + Dat_m : out; + Sel : out; + + -- Master inputs + Ack : in; + Dat_s : in; + end view; + alias Wishbone_Simple_SlaveView is Wishbone_Simple_MasterView'converse; + +end package; \ No newline at end of file diff --git a/Wishbone/vB3/WishboneCommon.vhdl b/Wishbone/vB3/WishboneCommon.vhdl new file mode 100644 index 0000000..3a62e19 --- /dev/null +++ b/Wishbone/vB3/WishboneCommon.vhdl @@ -0,0 +1,57 @@ +-- ============================================================================= +-- Authors: +-- Parham Soltani +-- +-- Package: +-- Common types for Wishbone interfaces +-- +-- Description: +-- Defines shared types like Addr_Type, Data_Type for use in Wishbone +-- records, following the Wishbone B.4 specification. +-- +-- License: +-- ============================================================================= +-- Copyright 2016-2025 Open Source VHDL Group +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +package WishboneCommon is + -- Common types (native VHDL-2019 bit types) + subtype Data_Type is bit_vector; + subtype Addr_Type is bit_vector; + subtype Sel_Type is bit_vector; + subtype Tgd_Type is bit_vector; -- Tag Data + subtype Tga_Type is bit_vector; -- Tag Address + subtype Tgc_Type is bit_vector; -- Tag Cycle + + -- Cycle Type Identifiers (CTI) + subtype Cti_Type is bit_vector(2 downto 0); + constant WB_CTI_CLASSIC : Cti_Type := "000"; -- Classic cycle + constant WB_CTI_CONST_BURST : Cti_Type := "001"; -- Constant address burst + constant WB_CTI_INCR_BURST : Cti_Type := "010"; -- Incrementing burst + constant WB_CTI_END_OF_BURST : Cti_Type := "111"; -- End of burst + + -- Burst Type Extension (BTE) + subtype Bte_Type is bit_vector(1 downto 0); + constant WB_BTE_LINEAR : Bte_Type := "00"; -- Linear burst + constant WB_BTE_WRAP_4 : Bte_Type := "01"; -- 4-beat wrap burst + constant WB_BTE_WRAP_8 : Bte_Type := "10"; -- 8-beat wrap burst + constant WB_BTE_WRAP_16 : Bte_Type := "11"; -- 16-beat wrap burst + + type Wishbone_System_Interface is record + Clk : bit; -- Clock + Rst : bit; -- Reset + end record; + +end package; \ No newline at end of file diff --git a/Wishbone/vB3/Wishbone_Generic.vhdl b/Wishbone/vB3/Wishbone_Generic.vhdl new file mode 100644 index 0000000..47f4f48 --- /dev/null +++ b/Wishbone/vB3/Wishbone_Generic.vhdl @@ -0,0 +1,79 @@ +-- ============================================================================= +-- Authors: +-- Parham Soltani +-- +-- Package: +-- Generic Wishbone interface for pre-constraining widths +-- +-- Description: +-- Uses spec-matching names (Addr, Sel, Dat, Cyc, Stb, etc.) +-- +-- License: +-- ============================================================================= +-- Copyright 2016-2025 Open Source VHDL Group +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +use work.Wishbone.all; + +package Wishbone_Generic is + generic ( + constant ADDRESS_BITS : positive; + constant DATA_BITS : positive; + constant TGD_BITS : positive := 1; + constant TGA_BITS : positive := 1; + constant TGC_BITS : positive := 1 + ); + + constant SEL_BITS : positive := DATA_BITS / 8; + + -- Full Wishbone interface with all optional signals + subtype Wishbone_SizedInterface is Wishbone_Interface( + Addr(ADDRESS_BITS - 1 downto 0), + Dat_m(DATA_BITS - 1 downto 0), + Dat_s(DATA_BITS - 1 downto 0), + Sel(SEL_BITS - 1 downto 0), + Tgd_m(TGD_BITS - 1 downto 0), + Tgd_s(TGD_BITS - 1 downto 0), + Tga(TGA_BITS - 1 downto 0), + Tgc(TGC_BITS - 1 downto 0) + ); + + subtype Wishbone_SizedInterface_Vector is Wishbone_Interface_Vector(open)( + Addr(ADDRESS_BITS - 1 downto 0), + Dat_m(DATA_BITS - 1 downto 0), + Dat_s(DATA_BITS - 1 downto 0), + Sel(SEL_BITS - 1 downto 0), + Tgd_m(TGD_BITS - 1 downto 0), + Tgd_s(TGD_BITS - 1 downto 0), + Tga(TGA_BITS - 1 downto 0), + Tgc(TGC_BITS - 1 downto 0) + ); + + -- Simplified Wishbone interface + subtype Wishbone_Simple_SizedInterface is Wishbone_Simple_Interface( + Addr(ADDRESS_BITS - 1 downto 0), + Dat_m(DATA_BITS - 1 downto 0), + Dat_s(DATA_BITS - 1 downto 0), + Sel(SEL_BITS - 1 downto 0) + ); + + subtype Wishbone_Simple_SizedInterface_Vector is Wishbone_Simple_Interface_Vector(open)( + Addr(ADDRESS_BITS - 1 downto 0), + Dat_m(DATA_BITS - 1 downto 0), + Dat_s(DATA_BITS - 1 downto 0), + Sel(SEL_BITS - 1 downto 0) + ); + +end package; \ No newline at end of file diff --git a/build.pro b/build.pro index 5cd91d5..860610b 100644 --- a/build.pro +++ b/build.pro @@ -52,3 +52,13 @@ analyze MIPI/M-PHY.vhdl # Miscellaneous interfaces analyze PoC/CSE.vhdl + +# Wishbone interfaces +analyze Wishbone/vB3/WishboneCommon.vhdl +analyze Wishbone/vB3/Wishbone.vhdl +analyze Wishbone/vB3/Wishbone_Generic.vhdl + +# Avalon interfaces +analyze Avalon/v1/AvalonMMCommon.vhdl +analyze Avalon/v1/AvalonMM.vhdl +analyze Avalon/v1/AvalonMM_Generic.vhdl \ No newline at end of file diff --git a/compileorder.list b/compileorder.list index afa443d..043225c 100644 --- a/compileorder.list +++ b/compileorder.list @@ -50,3 +50,14 @@ MIPI/M-PHY.vhdl # Miscellaneous interfaces PoC/CSE.vhdl + +# Wishbone B.3 Interfaces +Wishbone/vB3/WishboneCommon.vhdl +Wishbone/vB3/Wishbone.vhdl +Wishbone/vB3/Wishbone_Generic.vhdl + +# Avalon Memory-Mapped Interfaces +Avalon/v1/AvalonMMCommon.vhdl +Avalon/v1/AvalonMM.vhdl +Avalon/v1/AvalonMM_Generic.vhdl + From 468f2b8bdb2877c83eb6b4dd16f6b561d5f5630c Mon Sep 17 00:00:00 2001 From: parhamsoltani Date: Thu, 11 Dec 2025 01:08:45 +0330 Subject: [PATCH 4/8] minor change on compileorder --- build.pro | 2 +- compileorder.list | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/build.pro b/build.pro index 860610b..136ece0 100644 --- a/build.pro +++ b/build.pro @@ -59,6 +59,6 @@ analyze Wishbone/vB3/Wishbone.vhdl analyze Wishbone/vB3/Wishbone_Generic.vhdl # Avalon interfaces -analyze Avalon/v1/AvalonMMCommon.vhdl +analyze Avalon/v1/AvalonCommon.vhdl analyze Avalon/v1/AvalonMM.vhdl analyze Avalon/v1/AvalonMM_Generic.vhdl \ No newline at end of file diff --git a/compileorder.list b/compileorder.list index 043225c..793685a 100644 --- a/compileorder.list +++ b/compileorder.list @@ -57,7 +57,7 @@ Wishbone/vB3/Wishbone.vhdl Wishbone/vB3/Wishbone_Generic.vhdl # Avalon Memory-Mapped Interfaces -Avalon/v1/AvalonMMCommon.vhdl +Avalon/v1/AvalonCommon.vhdl Avalon/v1/AvalonMM.vhdl Avalon/v1/AvalonMM_Generic.vhdl From 7f3e47797464afa28edad2b965ac6114309c1224 Mon Sep 17 00:00:00 2001 From: parhamsoltani Date: Thu, 11 Dec 2025 10:49:34 +0330 Subject: [PATCH 5/8] updated wishbone using std_ulogic/std_ulogic_vector, and unsigned types with UpperCamelCase naming --- Wishbone/vB3/Wishbone.vhdl | 54 ++++++++++++++++-------------- Wishbone/vB3/WishboneCommon.vhdl | 26 ++++++++------ Wishbone/vB3/Wishbone_Generic.vhdl | 24 ++++++------- 3 files changed, 56 insertions(+), 48 deletions(-) diff --git a/Wishbone/vB3/Wishbone.vhdl b/Wishbone/vB3/Wishbone.vhdl index aa5be8a..afdae00 100644 --- a/Wishbone/vB3/Wishbone.vhdl +++ b/Wishbone/vB3/Wishbone.vhdl @@ -26,38 +26,42 @@ -- limitations under the License. -- ============================================================================= -use work.WishboneCommon.all; +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.WishboneCommon.all; package Wishbone is -- Classic Wishbone Interface (matching spec signal names) type Wishbone_Interface is record -- Master signals (outputs from master perspective) - Cyc : bit; -- CYC_O - Cycle - Stb : bit; -- STB_O - Strobe - We : bit; -- WE_O - Write Enable + Cyc : std_ulogic; -- CYC_O - Cycle + Stb : std_ulogic; -- STB_O - Strobe + We : std_ulogic; -- WE_O - Write Enable Addr : Addr_Type; -- ADR_O - Address - Dat_m : Data_Type; -- DAT_O - Data (Master to Slave) + DatM : Data_Type; -- DAT_O - Data (Master to Slave) Sel : Sel_Type; -- SEL_O - Select -- Slave signals (outputs from slave perspective) - Ack : bit; -- ACK_I - Acknowledge - Err : bit; -- ERR_I - Error - Rty : bit; -- RTY_I - Retry - Dat_s : Data_Type; -- DAT_I - Data (Slave to Master) + Ack : std_ulogic; -- ACK_I - Acknowledge + Err : std_ulogic; -- ERR_I - Error + Rty : std_ulogic; -- RTY_I - Retry + DatS : Data_Type; -- DAT_I - Data (Slave to Master) -- Optional signals for pipelined/burst modes Cti : Cti_Type; -- CTI_O - Cycle Type Identifier Bte : Bte_Type; -- BTE_O - Burst Type Extension -- Optional tag signals - Tgd_m : Tgd_Type; -- TGD_O - Tag Data (Master) - Tgd_s : Tgd_Type; -- TGD_I - Tag Data (Slave) + TgdM : Tgd_Type; -- TGD_O - Tag Data (Master) + TgdS : Tgd_Type; -- TGD_I - Tag Data (Slave) Tga : Tga_Type; -- TGA_O - Tag Address Tgc : Tgc_Type; -- TGC_O - Tag Cycle -- Optional signals - Lock : bit; -- LOCK_O - Lock - Stall : bit; -- STALL_I - Pipeline stall + Lock : std_ulogic; -- LOCK_O - Lock + Stall : std_ulogic; -- STALL_I - Pipeline stall end record; type Wishbone_Interface_Vector is array(natural range <>) of Wishbone_Interface; @@ -68,11 +72,11 @@ package Wishbone is Stb : out; We : out; Addr : out; - Dat_m : out; + DatM : out; Sel : out; Cti : out; Bte : out; - Tgd_m : out; + TgdM : out; Tga : out; Tgc : out; Lock : out; @@ -81,8 +85,8 @@ package Wishbone is Ack : in; Err : in; Rty : in; - Dat_s : in; - Tgd_s : in; + DatS : in; + TgdS : in; Stall : in; end view; alias Wishbone_SlaveView is Wishbone_MasterView'converse; @@ -90,16 +94,16 @@ package Wishbone is -- Simplified interface without optional signals type Wishbone_Simple_Interface is record -- Master signals - Cyc : bit; - Stb : bit; - We : bit; + Cyc : std_ulogic; + Stb : std_ulogic; + We : std_ulogic; Addr : Addr_Type; - Dat_m : Data_Type; + DatM : Data_Type; Sel : Sel_Type; -- Slave signals - Ack : bit; - Dat_s : Data_Type; + Ack : std_ulogic; + DatS : Data_Type; end record; type Wishbone_Simple_Interface_Vector is array(natural range <>) of Wishbone_Simple_Interface; @@ -109,12 +113,12 @@ package Wishbone is Stb : out; We : out; Addr : out; - Dat_m : out; + DatM : out; Sel : out; -- Master inputs Ack : in; - Dat_s : in; + DatS : in; end view; alias Wishbone_Simple_SlaveView is Wishbone_Simple_MasterView'converse; diff --git a/Wishbone/vB3/WishboneCommon.vhdl b/Wishbone/vB3/WishboneCommon.vhdl index 3a62e19..d169037 100644 --- a/Wishbone/vB3/WishboneCommon.vhdl +++ b/Wishbone/vB3/WishboneCommon.vhdl @@ -26,32 +26,36 @@ -- limitations under the License. -- ============================================================================= +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + package WishboneCommon is - -- Common types (native VHDL-2019 bit types) - subtype Data_Type is bit_vector; - subtype Addr_Type is bit_vector; - subtype Sel_Type is bit_vector; - subtype Tgd_Type is bit_vector; -- Tag Data - subtype Tga_Type is bit_vector; -- Tag Address - subtype Tgc_Type is bit_vector; -- Tag Cycle + -- Common types + subtype Data_Type is std_ulogic_vector; + subtype Addr_Type is unsigned; + subtype Sel_Type is std_ulogic_vector; + subtype Tgd_Type is std_ulogic_vector; -- Tag Data + subtype Tga_Type is std_ulogic_vector; -- Tag Address + subtype Tgc_Type is std_ulogic_vector; -- Tag Cycle -- Cycle Type Identifiers (CTI) - subtype Cti_Type is bit_vector(2 downto 0); + subtype Cti_Type is std_ulogic_vector(2 downto 0); constant WB_CTI_CLASSIC : Cti_Type := "000"; -- Classic cycle constant WB_CTI_CONST_BURST : Cti_Type := "001"; -- Constant address burst constant WB_CTI_INCR_BURST : Cti_Type := "010"; -- Incrementing burst constant WB_CTI_END_OF_BURST : Cti_Type := "111"; -- End of burst -- Burst Type Extension (BTE) - subtype Bte_Type is bit_vector(1 downto 0); + subtype Bte_Type is std_ulogic_vector(1 downto 0); constant WB_BTE_LINEAR : Bte_Type := "00"; -- Linear burst constant WB_BTE_WRAP_4 : Bte_Type := "01"; -- 4-beat wrap burst constant WB_BTE_WRAP_8 : Bte_Type := "10"; -- 8-beat wrap burst constant WB_BTE_WRAP_16 : Bte_Type := "11"; -- 16-beat wrap burst type Wishbone_System_Interface is record - Clk : bit; -- Clock - Rst : bit; -- Reset + Clk : std_ulogic; -- Clock + Rst : std_ulogic; -- Reset end record; end package; \ No newline at end of file diff --git a/Wishbone/vB3/Wishbone_Generic.vhdl b/Wishbone/vB3/Wishbone_Generic.vhdl index 47f4f48..280e577 100644 --- a/Wishbone/vB3/Wishbone_Generic.vhdl +++ b/Wishbone/vB3/Wishbone_Generic.vhdl @@ -41,22 +41,22 @@ package Wishbone_Generic is -- Full Wishbone interface with all optional signals subtype Wishbone_SizedInterface is Wishbone_Interface( Addr(ADDRESS_BITS - 1 downto 0), - Dat_m(DATA_BITS - 1 downto 0), - Dat_s(DATA_BITS - 1 downto 0), + DatM(DATA_BITS - 1 downto 0), + DatS(DATA_BITS - 1 downto 0), Sel(SEL_BITS - 1 downto 0), - Tgd_m(TGD_BITS - 1 downto 0), - Tgd_s(TGD_BITS - 1 downto 0), + TgdM(TGD_BITS - 1 downto 0), + TgdS(TGD_BITS - 1 downto 0), Tga(TGA_BITS - 1 downto 0), Tgc(TGC_BITS - 1 downto 0) ); subtype Wishbone_SizedInterface_Vector is Wishbone_Interface_Vector(open)( Addr(ADDRESS_BITS - 1 downto 0), - Dat_m(DATA_BITS - 1 downto 0), - Dat_s(DATA_BITS - 1 downto 0), + DatM(DATA_BITS - 1 downto 0), + DatS(DATA_BITS - 1 downto 0), Sel(SEL_BITS - 1 downto 0), - Tgd_m(TGD_BITS - 1 downto 0), - Tgd_s(TGD_BITS - 1 downto 0), + TgdM(TGD_BITS - 1 downto 0), + TgdS(TGD_BITS - 1 downto 0), Tga(TGA_BITS - 1 downto 0), Tgc(TGC_BITS - 1 downto 0) ); @@ -64,15 +64,15 @@ package Wishbone_Generic is -- Simplified Wishbone interface subtype Wishbone_Simple_SizedInterface is Wishbone_Simple_Interface( Addr(ADDRESS_BITS - 1 downto 0), - Dat_m(DATA_BITS - 1 downto 0), - Dat_s(DATA_BITS - 1 downto 0), + DatM(DATA_BITS - 1 downto 0), + DatS(DATA_BITS - 1 downto 0), Sel(SEL_BITS - 1 downto 0) ); subtype Wishbone_Simple_SizedInterface_Vector is Wishbone_Simple_Interface_Vector(open)( Addr(ADDRESS_BITS - 1 downto 0), - Dat_m(DATA_BITS - 1 downto 0), - Dat_s(DATA_BITS - 1 downto 0), + DatM(DATA_BITS - 1 downto 0), + DatS(DATA_BITS - 1 downto 0), Sel(SEL_BITS - 1 downto 0) ); From dbf4e24df918553094424abd468ba39ae7181a1e Mon Sep 17 00:00:00 2001 From: parhamsoltani Date: Thu, 11 Dec 2025 12:37:01 +0330 Subject: [PATCH 6/8] Revert "updated wishbone using std_ulogic/std_ulogic_vector, and unsigned types with UpperCamelCase naming" This reverts commit 7f3e47797464afa28edad2b965ac6114309c1224. --- Wishbone/vB3/Wishbone.vhdl | 54 ++++++++++++++---------------- Wishbone/vB3/WishboneCommon.vhdl | 26 ++++++-------- Wishbone/vB3/Wishbone_Generic.vhdl | 24 ++++++------- 3 files changed, 48 insertions(+), 56 deletions(-) diff --git a/Wishbone/vB3/Wishbone.vhdl b/Wishbone/vB3/Wishbone.vhdl index afdae00..aa5be8a 100644 --- a/Wishbone/vB3/Wishbone.vhdl +++ b/Wishbone/vB3/Wishbone.vhdl @@ -26,42 +26,38 @@ -- limitations under the License. -- ============================================================================= -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -use work.WishboneCommon.all; +use work.WishboneCommon.all; package Wishbone is -- Classic Wishbone Interface (matching spec signal names) type Wishbone_Interface is record -- Master signals (outputs from master perspective) - Cyc : std_ulogic; -- CYC_O - Cycle - Stb : std_ulogic; -- STB_O - Strobe - We : std_ulogic; -- WE_O - Write Enable + Cyc : bit; -- CYC_O - Cycle + Stb : bit; -- STB_O - Strobe + We : bit; -- WE_O - Write Enable Addr : Addr_Type; -- ADR_O - Address - DatM : Data_Type; -- DAT_O - Data (Master to Slave) + Dat_m : Data_Type; -- DAT_O - Data (Master to Slave) Sel : Sel_Type; -- SEL_O - Select -- Slave signals (outputs from slave perspective) - Ack : std_ulogic; -- ACK_I - Acknowledge - Err : std_ulogic; -- ERR_I - Error - Rty : std_ulogic; -- RTY_I - Retry - DatS : Data_Type; -- DAT_I - Data (Slave to Master) + Ack : bit; -- ACK_I - Acknowledge + Err : bit; -- ERR_I - Error + Rty : bit; -- RTY_I - Retry + Dat_s : Data_Type; -- DAT_I - Data (Slave to Master) -- Optional signals for pipelined/burst modes Cti : Cti_Type; -- CTI_O - Cycle Type Identifier Bte : Bte_Type; -- BTE_O - Burst Type Extension -- Optional tag signals - TgdM : Tgd_Type; -- TGD_O - Tag Data (Master) - TgdS : Tgd_Type; -- TGD_I - Tag Data (Slave) + Tgd_m : Tgd_Type; -- TGD_O - Tag Data (Master) + Tgd_s : Tgd_Type; -- TGD_I - Tag Data (Slave) Tga : Tga_Type; -- TGA_O - Tag Address Tgc : Tgc_Type; -- TGC_O - Tag Cycle -- Optional signals - Lock : std_ulogic; -- LOCK_O - Lock - Stall : std_ulogic; -- STALL_I - Pipeline stall + Lock : bit; -- LOCK_O - Lock + Stall : bit; -- STALL_I - Pipeline stall end record; type Wishbone_Interface_Vector is array(natural range <>) of Wishbone_Interface; @@ -72,11 +68,11 @@ package Wishbone is Stb : out; We : out; Addr : out; - DatM : out; + Dat_m : out; Sel : out; Cti : out; Bte : out; - TgdM : out; + Tgd_m : out; Tga : out; Tgc : out; Lock : out; @@ -85,8 +81,8 @@ package Wishbone is Ack : in; Err : in; Rty : in; - DatS : in; - TgdS : in; + Dat_s : in; + Tgd_s : in; Stall : in; end view; alias Wishbone_SlaveView is Wishbone_MasterView'converse; @@ -94,16 +90,16 @@ package Wishbone is -- Simplified interface without optional signals type Wishbone_Simple_Interface is record -- Master signals - Cyc : std_ulogic; - Stb : std_ulogic; - We : std_ulogic; + Cyc : bit; + Stb : bit; + We : bit; Addr : Addr_Type; - DatM : Data_Type; + Dat_m : Data_Type; Sel : Sel_Type; -- Slave signals - Ack : std_ulogic; - DatS : Data_Type; + Ack : bit; + Dat_s : Data_Type; end record; type Wishbone_Simple_Interface_Vector is array(natural range <>) of Wishbone_Simple_Interface; @@ -113,12 +109,12 @@ package Wishbone is Stb : out; We : out; Addr : out; - DatM : out; + Dat_m : out; Sel : out; -- Master inputs Ack : in; - DatS : in; + Dat_s : in; end view; alias Wishbone_Simple_SlaveView is Wishbone_Simple_MasterView'converse; diff --git a/Wishbone/vB3/WishboneCommon.vhdl b/Wishbone/vB3/WishboneCommon.vhdl index d169037..3a62e19 100644 --- a/Wishbone/vB3/WishboneCommon.vhdl +++ b/Wishbone/vB3/WishboneCommon.vhdl @@ -26,36 +26,32 @@ -- limitations under the License. -- ============================================================================= -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - package WishboneCommon is - -- Common types - subtype Data_Type is std_ulogic_vector; - subtype Addr_Type is unsigned; - subtype Sel_Type is std_ulogic_vector; - subtype Tgd_Type is std_ulogic_vector; -- Tag Data - subtype Tga_Type is std_ulogic_vector; -- Tag Address - subtype Tgc_Type is std_ulogic_vector; -- Tag Cycle + -- Common types (native VHDL-2019 bit types) + subtype Data_Type is bit_vector; + subtype Addr_Type is bit_vector; + subtype Sel_Type is bit_vector; + subtype Tgd_Type is bit_vector; -- Tag Data + subtype Tga_Type is bit_vector; -- Tag Address + subtype Tgc_Type is bit_vector; -- Tag Cycle -- Cycle Type Identifiers (CTI) - subtype Cti_Type is std_ulogic_vector(2 downto 0); + subtype Cti_Type is bit_vector(2 downto 0); constant WB_CTI_CLASSIC : Cti_Type := "000"; -- Classic cycle constant WB_CTI_CONST_BURST : Cti_Type := "001"; -- Constant address burst constant WB_CTI_INCR_BURST : Cti_Type := "010"; -- Incrementing burst constant WB_CTI_END_OF_BURST : Cti_Type := "111"; -- End of burst -- Burst Type Extension (BTE) - subtype Bte_Type is std_ulogic_vector(1 downto 0); + subtype Bte_Type is bit_vector(1 downto 0); constant WB_BTE_LINEAR : Bte_Type := "00"; -- Linear burst constant WB_BTE_WRAP_4 : Bte_Type := "01"; -- 4-beat wrap burst constant WB_BTE_WRAP_8 : Bte_Type := "10"; -- 8-beat wrap burst constant WB_BTE_WRAP_16 : Bte_Type := "11"; -- 16-beat wrap burst type Wishbone_System_Interface is record - Clk : std_ulogic; -- Clock - Rst : std_ulogic; -- Reset + Clk : bit; -- Clock + Rst : bit; -- Reset end record; end package; \ No newline at end of file diff --git a/Wishbone/vB3/Wishbone_Generic.vhdl b/Wishbone/vB3/Wishbone_Generic.vhdl index 280e577..47f4f48 100644 --- a/Wishbone/vB3/Wishbone_Generic.vhdl +++ b/Wishbone/vB3/Wishbone_Generic.vhdl @@ -41,22 +41,22 @@ package Wishbone_Generic is -- Full Wishbone interface with all optional signals subtype Wishbone_SizedInterface is Wishbone_Interface( Addr(ADDRESS_BITS - 1 downto 0), - DatM(DATA_BITS - 1 downto 0), - DatS(DATA_BITS - 1 downto 0), + Dat_m(DATA_BITS - 1 downto 0), + Dat_s(DATA_BITS - 1 downto 0), Sel(SEL_BITS - 1 downto 0), - TgdM(TGD_BITS - 1 downto 0), - TgdS(TGD_BITS - 1 downto 0), + Tgd_m(TGD_BITS - 1 downto 0), + Tgd_s(TGD_BITS - 1 downto 0), Tga(TGA_BITS - 1 downto 0), Tgc(TGC_BITS - 1 downto 0) ); subtype Wishbone_SizedInterface_Vector is Wishbone_Interface_Vector(open)( Addr(ADDRESS_BITS - 1 downto 0), - DatM(DATA_BITS - 1 downto 0), - DatS(DATA_BITS - 1 downto 0), + Dat_m(DATA_BITS - 1 downto 0), + Dat_s(DATA_BITS - 1 downto 0), Sel(SEL_BITS - 1 downto 0), - TgdM(TGD_BITS - 1 downto 0), - TgdS(TGD_BITS - 1 downto 0), + Tgd_m(TGD_BITS - 1 downto 0), + Tgd_s(TGD_BITS - 1 downto 0), Tga(TGA_BITS - 1 downto 0), Tgc(TGC_BITS - 1 downto 0) ); @@ -64,15 +64,15 @@ package Wishbone_Generic is -- Simplified Wishbone interface subtype Wishbone_Simple_SizedInterface is Wishbone_Simple_Interface( Addr(ADDRESS_BITS - 1 downto 0), - DatM(DATA_BITS - 1 downto 0), - DatS(DATA_BITS - 1 downto 0), + Dat_m(DATA_BITS - 1 downto 0), + Dat_s(DATA_BITS - 1 downto 0), Sel(SEL_BITS - 1 downto 0) ); subtype Wishbone_Simple_SizedInterface_Vector is Wishbone_Simple_Interface_Vector(open)( Addr(ADDRESS_BITS - 1 downto 0), - DatM(DATA_BITS - 1 downto 0), - DatS(DATA_BITS - 1 downto 0), + Dat_m(DATA_BITS - 1 downto 0), + Dat_s(DATA_BITS - 1 downto 0), Sel(SEL_BITS - 1 downto 0) ); From e4b0caf6a2aaca016bc11d451b4b6a6c6f2323f6 Mon Sep 17 00:00:00 2001 From: parhamsoltani Date: Thu, 11 Dec 2025 12:42:32 +0330 Subject: [PATCH 7/8] This reverts commit d05a9dfa1dbeca6c137467a2c9827fd5d0d6045a. --- Avalon/v1/AvalonCommon.vhdl | 47 ----------- Avalon/v1/AvalonMM.vhdl | 111 -------------------------- Avalon/v1/AvalonMM_Generic.vhdl | 71 ----------------- Avalon/v1/AvalonST.vhdl | 91 ---------------------- Avalon/v1/AvalonST_Generic.vhdl | 62 --------------- Wishbone/vB3/Wishbone.vhdl | 121 ----------------------------- Wishbone/vB3/WishboneCommon.vhdl | 57 -------------- Wishbone/vB3/Wishbone_Generic.vhdl | 79 ------------------- build.pro | 10 --- compileorder.list | 11 --- 10 files changed, 660 deletions(-) delete mode 100644 Avalon/v1/AvalonCommon.vhdl delete mode 100644 Avalon/v1/AvalonMM.vhdl delete mode 100644 Avalon/v1/AvalonMM_Generic.vhdl delete mode 100644 Avalon/v1/AvalonST.vhdl delete mode 100644 Avalon/v1/AvalonST_Generic.vhdl delete mode 100644 Wishbone/vB3/Wishbone.vhdl delete mode 100644 Wishbone/vB3/WishboneCommon.vhdl delete mode 100644 Wishbone/vB3/Wishbone_Generic.vhdl diff --git a/Avalon/v1/AvalonCommon.vhdl b/Avalon/v1/AvalonCommon.vhdl deleted file mode 100644 index a58c516..0000000 --- a/Avalon/v1/AvalonCommon.vhdl +++ /dev/null @@ -1,47 +0,0 @@ --- ============================================================================= --- Authors: --- Parham Soltani --- --- Package: --- Common types for Avalon Memory-Mapped (MM) interfaces --- --- Description: --- Defines shared types for use in Avalon-MM records --- --- License: --- ============================================================================= --- Copyright 2016-2025 Open Source VHDL Group --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -package AvalonCommon is - -- Common types (native VHDL-2019 bit types) - subtype Data_Type is bit_vector; - subtype Address_Type is bit_vector; - subtype ByteEnable_Type is bit_vector; - subtype BurstCount_Type is bit_vector; - - -- Avalon-MM Response - subtype Response_Type is bit_vector(1 downto 0); - constant AVALON_RESP_OKAY : Response_Type := "00"; - constant AVALON_RESP_RESERVED : Response_Type := "01"; - constant AVALON_RESP_SLAVEERROR : Response_Type := "10"; - constant AVALON_RESP_DECODEERROR : Response_Type := "11"; - - type Avalon_System_Interface is record - Clk : bit; - Reset : bit; - end record; - -end package; \ No newline at end of file diff --git a/Avalon/v1/AvalonMM.vhdl b/Avalon/v1/AvalonMM.vhdl deleted file mode 100644 index d3e6d40..0000000 --- a/Avalon/v1/AvalonMM.vhdl +++ /dev/null @@ -1,111 +0,0 @@ --- ============================================================================= --- Authors: --- Parham Soltani --- --- Package: --- VHDL-2019 Avalon Memory-Mapped (Avalon-MM) interface descriptions --- --- Description: --- Signal names match Avalon specification (address, writedata, readdata, etc.) --- Uses native VHDL-2019 bit types --- --- License: --- ============================================================================= --- Copyright 2016-2025 Open Source VHDL Group --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -use work.AvalonCommon.all; - -package AvalonMM is - -- Avalon Memory-Mapped Interface (matching spec signal names) - type AvalonMM_Interface is record - -- Master signals (names match Avalon spec exactly) - address : Address_Type; -- Address - read : bit; -- Read request - write : bit; -- Write request - writedata : Data_Type; -- Write data - byteenable : ByteEnable_Type; -- Byte enable - - -- Slave signals - readdata : Data_Type; -- Read data - readdatavalid : bit; -- Read data valid - waitrequest : bit; -- Wait request - response : Response_Type; -- Response - - -- Optional burst signals - burstcount : BurstCount_Type; -- Burst count - - -- Optional pipelining signals - writeresponsevalid : bit; -- Write response valid - - -- Optional lock signal - lock : bit; -- Lock - - -- Optional debug signals - debugaccess : bit; -- Debug access - end record; - type AvalonMM_Interface_Vector is array(natural range <>) of AvalonMM_Interface; - - -- Master view (from master's perspective) - view AvalonMM_MasterView of AvalonMM_Interface is - -- Master outputs - address : out; - read : out; - write : out; - writedata : out; - byteenable : out; - burstcount : out; - lock : out; - debugaccess : out; - - -- Master inputs (slave outputs) - readdata : in; - readdatavalid : in; - waitrequest : in; - response : in; - writeresponsevalid : in; - end view; - alias AvalonMM_SlaveView is AvalonMM_MasterView'converse; - - -- Simplified interface without optional signals - type AvalonMM_Simple_Interface is record - -- Master signals - address : Address_Type; - read : bit; - write : bit; - writedata : Data_Type; - byteenable : ByteEnable_Type; - - -- Slave signals - readdata : Data_Type; - waitrequest : bit; - end record; - type AvalonMM_Simple_Interface_Vector is array(natural range <>) of AvalonMM_Simple_Interface; - - view AvalonMM_Simple_MasterView of AvalonMM_Simple_Interface is - -- Master outputs - address : out; - read : out; - write : out; - writedata : out; - byteenable : out; - - -- Master inputs - readdata : in; - waitrequest : in; - end view; - alias AvalonMM_Simple_SlaveView is AvalonMM_Simple_MasterView'converse; - -end package; \ No newline at end of file diff --git a/Avalon/v1/AvalonMM_Generic.vhdl b/Avalon/v1/AvalonMM_Generic.vhdl deleted file mode 100644 index aab6ef9..0000000 --- a/Avalon/v1/AvalonMM_Generic.vhdl +++ /dev/null @@ -1,71 +0,0 @@ --- ============================================================================= --- Authors: --- Parham Soltani --- --- Package: --- Generic Avalon-MM interface for pre-constraining widths --- --- Description: --- Uses spec-matching names (address, writedata, readdata, byteenable, etc.) --- --- License: --- ============================================================================= --- Copyright 2016-2025 Open Source VHDL Group --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -use work.AvalonMM.all; - -package AvalonMM_Generic is - generic ( - constant ADDRESS_BITS : positive; - constant DATA_BITS : positive; - constant BURSTCOUNT_BITS : positive := 1 - ); - - constant BYTEENABLE_BITS : positive := DATA_BITS / 8; - - -- Full Avalon-MM interface with all optional signals - subtype AvalonMM_SizedInterface is AvalonMM_Interface( - address(ADDRESS_BITS - 1 downto 0), - writedata(DATA_BITS - 1 downto 0), - readdata(DATA_BITS - 1 downto 0), - byteenable(BYTEENABLE_BITS - 1 downto 0), - burstcount(BURSTCOUNT_BITS - 1 downto 0) - ); - - subtype AvalonMM_SizedInterface_Vector is AvalonMM_Interface_Vector(open)( - address(ADDRESS_BITS - 1 downto 0), - writedata(DATA_BITS - 1 downto 0), - readdata(DATA_BITS - 1 downto 0), - byteenable(BYTEENABLE_BITS - 1 downto 0), - burstcount(BURSTCOUNT_BITS - 1 downto 0) - ); - - -- Simplified Avalon-MM interface - subtype AvalonMM_Simple_SizedInterface is AvalonMM_Simple_Interface( - address(ADDRESS_BITS - 1 downto 0), - writedata(DATA_BITS - 1 downto 0), - readdata(DATA_BITS - 1 downto 0), - byteenable(BYTEENABLE_BITS - 1 downto 0) - ); - - subtype AvalonMM_Simple_SizedInterface_Vector is AvalonMM_Simple_Interface_Vector(open)( - address(ADDRESS_BITS - 1 downto 0), - writedata(DATA_BITS - 1 downto 0), - readdata(DATA_BITS - 1 downto 0), - byteenable(BYTEENABLE_BITS - 1 downto 0) - ); - -end package; \ No newline at end of file diff --git a/Avalon/v1/AvalonST.vhdl b/Avalon/v1/AvalonST.vhdl deleted file mode 100644 index d9791a5..0000000 --- a/Avalon/v1/AvalonST.vhdl +++ /dev/null @@ -1,91 +0,0 @@ --- ============================================================================= --- Authors: --- Parham Soltani --- --- Package: --- VHDL-2019 Avalon Streaming (Avalon-ST) interface descriptions --- --- Description: --- Signal names match Avalon-ST specification (data, valid, ready, etc.) --- Uses native VHDL-2019 bit types --- --- License: --- ============================================================================= --- Copyright 2016-2025 Open Source VHDL Group --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -use work.AvalonCommon.all; - -package AvalonST is - -- Avalon Streaming Interface (matching spec signal names) - type AvalonST_Interface is record - -- Handshake signals - valid : bit; -- Valid - ready : bit; -- Ready - - -- Payload signals - data : Data_Type; -- Data - - -- Packet signals - startofpacket : bit; -- Start of packet - endofpacket : bit; -- End of packet - empty : bit_vector; -- Empty (number of empty symbols) - - -- Error signal - error : bit_vector; -- Error - - -- Channel signal - channel : bit_vector; -- Channel - end record; - type AvalonST_Interface_Vector is array(natural range <>) of AvalonST_Interface; - - -- Source view (from source's perspective) - view AvalonST_SourceView of AvalonST_Interface is - -- Source outputs - valid : out; - data : out; - startofpacket : out; - endofpacket : out; - empty : out; - error : out; - channel : out; - - -- Source inputs (sink outputs) - ready : in; - end view; - alias AvalonST_SinkView is AvalonST_SourceView'converse; - - -- Simplified interface without optional signals - type AvalonST_Simple_Interface is record - -- Handshake signals - valid : bit; - ready : bit; - - -- Payload signal - data : Data_Type; - end record; - type AvalonST_Simple_Interface_Vector is array(natural range <>) of AvalonST_Simple_Interface; - - view AvalonST_Simple_SourceView of AvalonST_Simple_Interface is - -- Source outputs - valid : out; - data : out; - - -- Source inputs - ready : in; - end view; - alias AvalonST_Simple_SinkView is AvalonST_Simple_SourceView'converse; - -end package; \ No newline at end of file diff --git a/Avalon/v1/AvalonST_Generic.vhdl b/Avalon/v1/AvalonST_Generic.vhdl deleted file mode 100644 index fca699e..0000000 --- a/Avalon/v1/AvalonST_Generic.vhdl +++ /dev/null @@ -1,62 +0,0 @@ --- ============================================================================= --- Authors: --- Parham Soltani --- --- Package: --- Generic Avalon-ST interface descriptions for pre-constraining --- --- Description: --- Uses spec-matching names (data, valid, ready, channel, etc.) --- --- License: --- ============================================================================= --- Copyright 2016-2025 Open Source VHDL Group --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -use work.AvalonST.all; - -package AvalonST_Generic is - generic ( - constant DATA_BITS : positive; - constant EMPTY_BITS : positive := 1; - constant ERROR_BITS : positive := 1; - constant CHANNEL_BITS : positive := 1 - ); - - -- Full Avalon-ST interface with all optional signals - subtype AvalonST_SizedInterface is AvalonST_Interface( - data(DATA_BITS - 1 downto 0), - empty(EMPTY_BITS - 1 downto 0), - error(ERROR_BITS - 1 downto 0), - channel(CHANNEL_BITS - 1 downto 0) - ); - - subtype AvalonST_SizedInterface_Vector is AvalonST_Interface_Vector(open)( - data(DATA_BITS - 1 downto 0), - empty(EMPTY_BITS - 1 downto 0), - error(ERROR_BITS - 1 downto 0), - channel(CHANNEL_BITS - 1 downto 0) - ); - - -- Simplified Avalon-ST interface - subtype AvalonST_Simple_SizedInterface is AvalonST_Simple_Interface( - data(DATA_BITS - 1 downto 0) - ); - - subtype AvalonST_Simple_SizedInterface_Vector is AvalonST_Simple_Interface_Vector(open)( - data(DATA_BITS - 1 downto 0) - ); - -end package; \ No newline at end of file diff --git a/Wishbone/vB3/Wishbone.vhdl b/Wishbone/vB3/Wishbone.vhdl deleted file mode 100644 index aa5be8a..0000000 --- a/Wishbone/vB3/Wishbone.vhdl +++ /dev/null @@ -1,121 +0,0 @@ --- ============================================================================= --- Authors: --- Parham Soltani --- --- Package: --- VHDL-2019 Wishbone interface descriptions --- --- Description: --- Signal names match Wishbone B.4 specification (Cyc, Stb, Ack, Err, etc.) --- Uses native VHDL-2019 bit types --- --- License: --- ============================================================================= --- Copyright 2016-2025 Open Source VHDL Group --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -use work.WishboneCommon.all; - -package Wishbone is - -- Classic Wishbone Interface (matching spec signal names) - type Wishbone_Interface is record - -- Master signals (outputs from master perspective) - Cyc : bit; -- CYC_O - Cycle - Stb : bit; -- STB_O - Strobe - We : bit; -- WE_O - Write Enable - Addr : Addr_Type; -- ADR_O - Address - Dat_m : Data_Type; -- DAT_O - Data (Master to Slave) - Sel : Sel_Type; -- SEL_O - Select - - -- Slave signals (outputs from slave perspective) - Ack : bit; -- ACK_I - Acknowledge - Err : bit; -- ERR_I - Error - Rty : bit; -- RTY_I - Retry - Dat_s : Data_Type; -- DAT_I - Data (Slave to Master) - - -- Optional signals for pipelined/burst modes - Cti : Cti_Type; -- CTI_O - Cycle Type Identifier - Bte : Bte_Type; -- BTE_O - Burst Type Extension - - -- Optional tag signals - Tgd_m : Tgd_Type; -- TGD_O - Tag Data (Master) - Tgd_s : Tgd_Type; -- TGD_I - Tag Data (Slave) - Tga : Tga_Type; -- TGA_O - Tag Address - Tgc : Tgc_Type; -- TGC_O - Tag Cycle - - -- Optional signals - Lock : bit; -- LOCK_O - Lock - Stall : bit; -- STALL_I - Pipeline stall - end record; - type Wishbone_Interface_Vector is array(natural range <>) of Wishbone_Interface; - - -- Master view (from master's perspective) - view Wishbone_MasterView of Wishbone_Interface is - -- Master outputs - Cyc : out; - Stb : out; - We : out; - Addr : out; - Dat_m : out; - Sel : out; - Cti : out; - Bte : out; - Tgd_m : out; - Tga : out; - Tgc : out; - Lock : out; - - -- Master inputs (slave outputs) - Ack : in; - Err : in; - Rty : in; - Dat_s : in; - Tgd_s : in; - Stall : in; - end view; - alias Wishbone_SlaveView is Wishbone_MasterView'converse; - - -- Simplified interface without optional signals - type Wishbone_Simple_Interface is record - -- Master signals - Cyc : bit; - Stb : bit; - We : bit; - Addr : Addr_Type; - Dat_m : Data_Type; - Sel : Sel_Type; - - -- Slave signals - Ack : bit; - Dat_s : Data_Type; - end record; - type Wishbone_Simple_Interface_Vector is array(natural range <>) of Wishbone_Simple_Interface; - - view Wishbone_Simple_MasterView of Wishbone_Simple_Interface is - -- Master outputs - Cyc : out; - Stb : out; - We : out; - Addr : out; - Dat_m : out; - Sel : out; - - -- Master inputs - Ack : in; - Dat_s : in; - end view; - alias Wishbone_Simple_SlaveView is Wishbone_Simple_MasterView'converse; - -end package; \ No newline at end of file diff --git a/Wishbone/vB3/WishboneCommon.vhdl b/Wishbone/vB3/WishboneCommon.vhdl deleted file mode 100644 index 3a62e19..0000000 --- a/Wishbone/vB3/WishboneCommon.vhdl +++ /dev/null @@ -1,57 +0,0 @@ --- ============================================================================= --- Authors: --- Parham Soltani --- --- Package: --- Common types for Wishbone interfaces --- --- Description: --- Defines shared types like Addr_Type, Data_Type for use in Wishbone --- records, following the Wishbone B.4 specification. --- --- License: --- ============================================================================= --- Copyright 2016-2025 Open Source VHDL Group --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -package WishboneCommon is - -- Common types (native VHDL-2019 bit types) - subtype Data_Type is bit_vector; - subtype Addr_Type is bit_vector; - subtype Sel_Type is bit_vector; - subtype Tgd_Type is bit_vector; -- Tag Data - subtype Tga_Type is bit_vector; -- Tag Address - subtype Tgc_Type is bit_vector; -- Tag Cycle - - -- Cycle Type Identifiers (CTI) - subtype Cti_Type is bit_vector(2 downto 0); - constant WB_CTI_CLASSIC : Cti_Type := "000"; -- Classic cycle - constant WB_CTI_CONST_BURST : Cti_Type := "001"; -- Constant address burst - constant WB_CTI_INCR_BURST : Cti_Type := "010"; -- Incrementing burst - constant WB_CTI_END_OF_BURST : Cti_Type := "111"; -- End of burst - - -- Burst Type Extension (BTE) - subtype Bte_Type is bit_vector(1 downto 0); - constant WB_BTE_LINEAR : Bte_Type := "00"; -- Linear burst - constant WB_BTE_WRAP_4 : Bte_Type := "01"; -- 4-beat wrap burst - constant WB_BTE_WRAP_8 : Bte_Type := "10"; -- 8-beat wrap burst - constant WB_BTE_WRAP_16 : Bte_Type := "11"; -- 16-beat wrap burst - - type Wishbone_System_Interface is record - Clk : bit; -- Clock - Rst : bit; -- Reset - end record; - -end package; \ No newline at end of file diff --git a/Wishbone/vB3/Wishbone_Generic.vhdl b/Wishbone/vB3/Wishbone_Generic.vhdl deleted file mode 100644 index 47f4f48..0000000 --- a/Wishbone/vB3/Wishbone_Generic.vhdl +++ /dev/null @@ -1,79 +0,0 @@ --- ============================================================================= --- Authors: --- Parham Soltani --- --- Package: --- Generic Wishbone interface for pre-constraining widths --- --- Description: --- Uses spec-matching names (Addr, Sel, Dat, Cyc, Stb, etc.) --- --- License: --- ============================================================================= --- Copyright 2016-2025 Open Source VHDL Group --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ============================================================================= - -use work.Wishbone.all; - -package Wishbone_Generic is - generic ( - constant ADDRESS_BITS : positive; - constant DATA_BITS : positive; - constant TGD_BITS : positive := 1; - constant TGA_BITS : positive := 1; - constant TGC_BITS : positive := 1 - ); - - constant SEL_BITS : positive := DATA_BITS / 8; - - -- Full Wishbone interface with all optional signals - subtype Wishbone_SizedInterface is Wishbone_Interface( - Addr(ADDRESS_BITS - 1 downto 0), - Dat_m(DATA_BITS - 1 downto 0), - Dat_s(DATA_BITS - 1 downto 0), - Sel(SEL_BITS - 1 downto 0), - Tgd_m(TGD_BITS - 1 downto 0), - Tgd_s(TGD_BITS - 1 downto 0), - Tga(TGA_BITS - 1 downto 0), - Tgc(TGC_BITS - 1 downto 0) - ); - - subtype Wishbone_SizedInterface_Vector is Wishbone_Interface_Vector(open)( - Addr(ADDRESS_BITS - 1 downto 0), - Dat_m(DATA_BITS - 1 downto 0), - Dat_s(DATA_BITS - 1 downto 0), - Sel(SEL_BITS - 1 downto 0), - Tgd_m(TGD_BITS - 1 downto 0), - Tgd_s(TGD_BITS - 1 downto 0), - Tga(TGA_BITS - 1 downto 0), - Tgc(TGC_BITS - 1 downto 0) - ); - - -- Simplified Wishbone interface - subtype Wishbone_Simple_SizedInterface is Wishbone_Simple_Interface( - Addr(ADDRESS_BITS - 1 downto 0), - Dat_m(DATA_BITS - 1 downto 0), - Dat_s(DATA_BITS - 1 downto 0), - Sel(SEL_BITS - 1 downto 0) - ); - - subtype Wishbone_Simple_SizedInterface_Vector is Wishbone_Simple_Interface_Vector(open)( - Addr(ADDRESS_BITS - 1 downto 0), - Dat_m(DATA_BITS - 1 downto 0), - Dat_s(DATA_BITS - 1 downto 0), - Sel(SEL_BITS - 1 downto 0) - ); - -end package; \ No newline at end of file diff --git a/build.pro b/build.pro index 136ece0..5cd91d5 100644 --- a/build.pro +++ b/build.pro @@ -52,13 +52,3 @@ analyze MIPI/M-PHY.vhdl # Miscellaneous interfaces analyze PoC/CSE.vhdl - -# Wishbone interfaces -analyze Wishbone/vB3/WishboneCommon.vhdl -analyze Wishbone/vB3/Wishbone.vhdl -analyze Wishbone/vB3/Wishbone_Generic.vhdl - -# Avalon interfaces -analyze Avalon/v1/AvalonCommon.vhdl -analyze Avalon/v1/AvalonMM.vhdl -analyze Avalon/v1/AvalonMM_Generic.vhdl \ No newline at end of file diff --git a/compileorder.list b/compileorder.list index 793685a..afa443d 100644 --- a/compileorder.list +++ b/compileorder.list @@ -50,14 +50,3 @@ MIPI/M-PHY.vhdl # Miscellaneous interfaces PoC/CSE.vhdl - -# Wishbone B.3 Interfaces -Wishbone/vB3/WishboneCommon.vhdl -Wishbone/vB3/Wishbone.vhdl -Wishbone/vB3/Wishbone_Generic.vhdl - -# Avalon Memory-Mapped Interfaces -Avalon/v1/AvalonCommon.vhdl -Avalon/v1/AvalonMM.vhdl -Avalon/v1/AvalonMM_Generic.vhdl - From fa9d0ac5f15a6bcd3312f58ae1c7fc72b8c6453b Mon Sep 17 00:00:00 2001 From: parhamsoltani Date: Tue, 6 Jan 2026 16:09:29 +0330 Subject: [PATCH 8/8] Add PCI Express (PCIe) 4.0 interface support --- HighSpeed/PCIe/v4/PCIe.vhdl | 213 ++++++++++++++++++++++++++++++ HighSpeed/PCIe/v4/PCIeCommon.vhdl | 155 ++++++++++++++++++++++ build.pro | 4 + compileorder.list | 4 + 4 files changed, 376 insertions(+) create mode 100644 HighSpeed/PCIe/v4/PCIe.vhdl create mode 100644 HighSpeed/PCIe/v4/PCIeCommon.vhdl diff --git a/HighSpeed/PCIe/v4/PCIe.vhdl b/HighSpeed/PCIe/v4/PCIe.vhdl new file mode 100644 index 0000000..31cb7bf --- /dev/null +++ b/HighSpeed/PCIe/v4/PCIe.vhdl @@ -0,0 +1,213 @@ +-- ============================================================================= +-- Authors: +-- Parham Soltani +-- +-- Package: +-- PCI Express Transaction Layer interface types +-- +-- Description: +-- Following the PCIe 4.0 specification. +-- +-- License: +-- ==================================================================================================================== -- +-- Copyright 2016-2025 Open Source VHDL Group -- +-- -- +-- Licensed under the Apache License, Version 2.0 (the "License"); -- +-- you may not use this file except in compliance with the License. -- +-- You may obtain a copy of the License at -- +-- -- +-- http://www.apache.org/licenses/LICENSE-2.0 -- +-- -- +-- Unless required by applicable law or agreed to in writing, software -- +-- distributed under the License is distributed on an "AS IS" BASIS, -- +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- +-- See the License for the specific language governing permissions and -- +-- limitations under the License. -- +-- ==================================================================================================================== -- + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library Interfaces; +use Interfaces.PCIe.v4.PCIeCommon.all; + +package PCIe is + + -- ============================================================================================================ + -- Transaction Layer - Transmit Interface (TLP TX) + -- ============================================================================================================ + + type t_PCIe_TLP_TX is record + -- Control + valid : std_logic; -- Data valid + ready : std_logic; -- Ready to accept data (backpressure) + sop : std_logic; -- Start of Packet + eop : std_logic; -- End of Packet + + -- TLP Header + header : t_PCIe_TLP_Header; + + -- Payload Data (256-bit for Gen3/Gen4) + data : std_logic_vector(255 downto 0); + keep : std_logic_vector(31 downto 0); -- Byte valid indicators + + -- Error Signaling + err : std_logic; -- Error in TLP + poisoned : std_logic; -- Poisoned TLP + end record; + + -- View from Master (endpoint transmitting TLP) + subtype t_PCIe_TLP_TX_m2s is t_PCIe_TLP_TX; + alias t_PCIe_TLP_TX_Master is t_PCIe_TLP_TX_m2s; + + -- View from Slave (endpoint receiving TLP) + subtype t_PCIe_TLP_TX_s2m is t_PCIe_TLP_TX; + alias t_PCIe_TLP_TX_Slave is t_PCIe_TLP_TX_s2m; + + -- ============================================================================================================ + -- Transaction Layer - Receive Interface (TLP RX) + -- ============================================================================================================ + + type t_PCIe_TLP_RX is record + -- Control + valid : std_logic; + ready : std_logic; + sop : std_logic; + eop : std_logic; + + -- TLP Header + header : t_PCIe_TLP_Header; + + -- Payload Data + data : std_logic_vector(255 downto 0); + keep : std_logic_vector(31 downto 0); + + -- Status + bar_hit : std_logic_vector(6 downto 0); -- Which BAR was hit + err : std_logic; + poisoned : std_logic; + end record; + + subtype t_PCIe_TLP_RX_m2s is t_PCIe_TLP_RX; + alias t_PCIe_TLP_RX_Master is t_PCIe_TLP_RX_m2s; + + subtype t_PCIe_TLP_RX_s2m is t_PCIe_TLP_RX; + alias t_PCIe_TLP_RX_Slave is t_PCIe_TLP_RX_s2m; + + -- ============================================================================================================ + -- Configuration Space Interface + -- ============================================================================================================ + + type t_PCIe_Config is record + -- Device Identification + vendor_id : std_logic_vector(15 downto 0); + device_id : std_logic_vector(15 downto 0); + revision_id : std_logic_vector(7 downto 0); + class_code : std_logic_vector(23 downto 0); + + -- BAR Configuration + bar_enabled : std_logic_vector(5 downto 0); + bar_type : std_logic_vector(5 downto 0); -- 0=32-bit, 1=64-bit + + -- Link Status + link_up : std_logic; + link_width : t_PCIe_LinkWidth; + link_speed : std_logic_vector(3 downto 0); -- Gen1/2/3/4 + + -- Power Management + power_state : t_PCIe_PowerState; + + -- Interrupts + msi_enabled : std_logic; + msix_enabled : std_logic; + max_payload_size: std_logic_vector(2 downto 0); -- 128/256/512/1024/2048/4096 + max_read_req : std_logic_vector(2 downto 0); + end record; + + -- ============================================================================================================ + -- Physical Layer Interface (for reference - typically handled by PHY IP) + -- ============================================================================================================ + + type t_PCIe_Physical_Lane is record + tx_p : std_logic; -- Differential TX positive + tx_n : std_logic; -- Differential TX negative + rx_p : std_logic; -- Differential RX positive + rx_n : std_logic; -- Differential RX negative + end record; + + type t_PCIe_Physical_Lane_Vector is array(natural range <>) of t_PCIe_Physical_Lane; + + -- ============================================================================================================ + -- Helper Functions + -- ============================================================================================================ + + function create_tlp_header( + tlp_type : t_PCIe_TLP_Type; + address : std_logic_vector(63 downto 2); + length : natural; + requester_id: std_logic_vector(15 downto 0); + tag : std_logic_vector(7 downto 0); + be_first : std_logic_vector(3 downto 0) := "1111"; + be_last : std_logic_vector(3 downto 0) := "1111" + ) return t_PCIe_TLP_Header; + +end package; + +package body PCIe is + + function create_tlp_header( + tlp_type : t_PCIe_TLP_Type; + address : std_logic_vector(63 downto 2); + length : natural; + requester_id: std_logic_vector(15 downto 0); + tag : std_logic_vector(7 downto 0); + be_first : std_logic_vector(3 downto 0) := "1111"; + be_last : std_logic_vector(3 downto 0) := "1111" + ) return t_PCIe_TLP_Header is + variable header : t_PCIe_TLP_Header; + begin + -- Set format and type based on TLP type + case tlp_type is + when MRd => + if address(63 downto 32) = x"00000000" then + header.fmt := "00"; -- 3DW header, no data + else + header.fmt := "01"; -- 4DW header, no data + end if; + header.pkt_type := "00000"; + + when MWr => + if address(63 downto 32) = x"00000000" then + header.fmt := "10"; -- 3DW header, with data + else + header.fmt := "11"; -- 4DW header, with data + end if; + header.pkt_type := "00000"; + + when CplD => + header.fmt := "10"; + header.pkt_type := "01010"; + + when others => + header.fmt := "00"; + header.pkt_type := "00000"; + end case; + + header.tc := "000"; -- Traffic Class 0 + header.attr := "000"; + header.th := '0'; + header.td := '0'; + header.ep := '0'; + header.length := std_logic_vector(to_unsigned(length, 10)); + header.requester_id:= requester_id; + header.tag := tag; + header.be_first := be_first; + header.be_last := be_last; + header.address := address; + + return header; + end function; + +end package body; diff --git a/HighSpeed/PCIe/v4/PCIeCommon.vhdl b/HighSpeed/PCIe/v4/PCIeCommon.vhdl new file mode 100644 index 0000000..ce46e9b --- /dev/null +++ b/HighSpeed/PCIe/v4/PCIeCommon.vhdl @@ -0,0 +1,155 @@ +-- ============================================================================= +-- Authors: +-- Parham Soltani +-- +-- Package: +-- Common types, constants, and enums for PCI Express interfaces +-- +-- Description: +-- Following the PCIe 4.0 specification. +-- +-- License: +-- ==================================================================================================================== -- +-- Copyright 2016-2025 Open Source VHDL Group -- +-- -- +-- Licensed under the Apache License, Version 2.0 (the "License"); -- +-- you may not use this file except in compliance with the License. -- +-- You may obtain a copy of the License at -- +-- -- +-- http://www.apache.org/licenses/LICENSE-2.0 -- +-- -- +-- Unless required by applicable law or agreed to in writing, software -- +-- distributed under the License is distributed on an "AS IS" BASIS, -- +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- +-- See the License for the specific language governing permissions and -- +-- limitations under the License. -- +-- ==================================================================================================================== -- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package PCIeCommon is + -- Link speeds + constant PCIE_GEN1_SPEED : natural := 2_500; -- Mbps per lane + constant PCIE_GEN2_SPEED : natural := 5_000; -- Mbps per lane + constant PCIE_GEN3_SPEED : natural := 8_000; -- Mbps per lane + constant PCIE_GEN4_SPEED : natural := 16_000; -- Mbps per lane + + -- Link widths + type t_PCIe_LinkWidth is (x1, x2, x4, x8, x16); + + function to_lanes(width : t_PCIe_LinkWidth) return positive; + + -- TLP Packet Types + type t_PCIe_TLP_Type is ( + MRd, -- Memory Read Request + MRdLk, -- Memory Read Request - Locked + MWr, -- Memory Write Request + IORd, -- I/O Read Request + IOWr, -- I/O Write Request + CfgRd0, -- Configuration Read Type 0 + CfgWr0, -- Configuration Write Type 0 + CfgRd1, -- Configuration Read Type 1 + CfgWr1, -- Configuration Write Type 1 + Msg, -- Message Request + MsgD, -- Message Request with Data + Cpl, -- Completion without Data + CplD, -- Completion with Data + CplLk, -- Completion for Locked Memory Read + CplDLk -- Completion for Locked Memory Read with Data + ); + + -- Transaction Layer Packet Header (32-bit aligned) + type t_PCIe_TLP_Header is record + fmt : std_logic_vector(1 downto 0); -- Format + pkt_type : std_logic_vector(4 downto 0); -- Type + tc : std_logic_vector(2 downto 0); -- Traffic Class + attr : std_logic_vector(2 downto 0); -- Attributes + th : std_logic; -- TLP Processing Hints + td : std_logic; -- TLP Digest Present + ep : std_logic; -- Poisoned Data + length : std_logic_vector(9 downto 0); -- Length in DW + requester_id: std_logic_vector(15 downto 0); -- Bus:Dev:Func + tag : std_logic_vector(7 downto 0); -- Transaction tag + be_last : std_logic_vector(3 downto 0); -- Last DW Byte Enable + be_first : std_logic_vector(3 downto 0); -- First DW Byte Enable + address : std_logic_vector(63 downto 2); -- 64-bit address (DW aligned) + end record; + + -- DLLP (Data Link Layer Packet) Types + type t_PCIe_DLLP_Type is ( + Ack, + Nak, + PM_Enter_L1, + PM_Enter_L23, + PM_Active_State_Request_L1, + PM_Request_Ack, + Vendor_Specific, + NOP, + FC_Init1, + FC_Init2, + FC_Update_P, + FC_Update_NP, + FC_Update_Cpl + ); + + -- Flow Control Credit Types + type t_PCIe_FC_Type is (Posted, NonPosted, Completion); + + -- Flow Control Credits + type t_PCIe_FlowControl is record + fc_type : t_PCIe_FC_Type; + hdr_credits : std_logic_vector(7 downto 0); + data_credits: std_logic_vector(11 downto 0); + end record; + + -- Link Training and Status State Machine (LTSSM) States + type t_PCIe_LTSSM_State is ( + Detect_Quiet, + Detect_Active, + Polling_Active, + Polling_Compliance, + Polling_Configuration, + Configuration_Linkwidth_Start, + Configuration_Linkwidth_Accept, + Configuration_Lanenum_Wait, + Configuration_Lanenum_Accept, + Configuration_Complete, + Configuration_Idle, + Recovery_RcvrLock, + Recovery_RcvrCfg, + Recovery_Idle, + L0, + L0s, + L1_Idle, + L1_Substate, + L2_Idle, + L2_TransmitWake, + Disabled_Idle, + Disabled_LinkWidth_Start, + Loopback_Entry, + Loopback_Active, + Loopback_Exit, + Hot_Reset + ); + + -- Power Management States + type t_PCIe_PowerState is (L0, L0s, L1, L2, L3); + +end package; + +package body PCIeCommon is + + function to_lanes(width : t_PCIe_LinkWidth) return positive is + begin + case width is + when x1 => return 1; + when x2 => return 2; + when x4 => return 4; + when x8 => return 8; + when x16 => return 16; + end case; + end function; + +end package body; diff --git a/build.pro b/build.pro index 5cd91d5..34bbd30 100644 --- a/build.pro +++ b/build.pro @@ -52,3 +52,7 @@ analyze MIPI/M-PHY.vhdl # Miscellaneous interfaces analyze PoC/CSE.vhdl + +# High-speed serial interfaces - PCI Express +analyze HighSpeed/PCIe/v4/PCIeCommon.vhdl +analyze HighSpeed/PCIe/v4/PCIe.vhdl diff --git a/compileorder.list b/compileorder.list index afa443d..73ad8f1 100644 --- a/compileorder.list +++ b/compileorder.list @@ -50,3 +50,7 @@ MIPI/M-PHY.vhdl # Miscellaneous interfaces PoC/CSE.vhdl + +# High-speed serial interfaces - PCI Express +HighSpeed/PCIe/v4/PCIeCommon.vhdl +HighSpeed/PCIe/v4/PCIe.vhdl