diff --git a/AMBA/AXI/v4/AXI4.vhdl b/AMBA/AXI/v4/AXI4.vhdl index 0f887c2..8b521f4 100644 --- a/AMBA/AXI/v4/AXI4.vhdl +++ b/AMBA/AXI/v4/AXI4.vhdl @@ -85,8 +85,8 @@ package Axi4 is type Axi4_ReadData_Interface is record -- Handshake signals - Valid : std_ulogic; - Ready : std_ulogic; + Valid : std_ulogic; + Ready : std_ulogic; -- Payload signals ID : ID_Type; diff --git a/AMBA/AXI/v4/AXI4_Generic.vhdl b/AMBA/AXI/v4/AXI4_Generic.vhdl index d03b4c8..8b4689f 100644 --- a/AMBA/AXI/v4/AXI4_Generic.vhdl +++ b/AMBA/AXI/v4/AXI4_Generic.vhdl @@ -32,11 +32,12 @@ package Axi4_Generic is generic ( constant ADDRESS_BITS : positive; constant DATA_BITS : positive; - constant STROBE_BITS : positive := DATA_BITS / 8; constant ID_BITS : positive; constant USER_BITS : positive ); + constant STROBE_BITS : positive := DATA_BITS / 8; + subtype Axi4_Address_SizedInterface is Axi4_Address_Interface( ID(ID_BITS - 1 downto 0), Address(ADDRESS_BITS - 1 downto 0), @@ -86,7 +87,7 @@ package Axi4_Generic is User(USER_BITS - 1 downto 0) ) ); - + subtype Axi4_SizedInterface_Vector is Axi4_Interface_Vector(open)( WriteAddress( ID(ID_BITS - 1 downto 0), diff --git a/HighSpeed/PCIe/v4/PCIe.vhdl b/HighSpeed/PCIe/v4/PCIe.vhdl new file mode 100644 index 0000000..31cb7bf --- /dev/null +++ b/HighSpeed/PCIe/v4/PCIe.vhdl @@ -0,0 +1,213 @@ +-- ============================================================================= +-- Authors: +-- Parham Soltani +-- +-- Package: +-- PCI Express Transaction Layer interface types +-- +-- Description: +-- Following the PCIe 4.0 specification. +-- +-- License: +-- ==================================================================================================================== -- +-- Copyright 2016-2025 Open Source VHDL Group -- +-- -- +-- Licensed under the Apache License, Version 2.0 (the "License"); -- +-- you may not use this file except in compliance with the License. -- +-- You may obtain a copy of the License at -- +-- -- +-- http://www.apache.org/licenses/LICENSE-2.0 -- +-- -- +-- Unless required by applicable law or agreed to in writing, software -- +-- distributed under the License is distributed on an "AS IS" BASIS, -- +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- +-- See the License for the specific language governing permissions and -- +-- limitations under the License. -- +-- ==================================================================================================================== -- + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library Interfaces; +use Interfaces.PCIe.v4.PCIeCommon.all; + +package PCIe is + + -- ============================================================================================================ + -- Transaction Layer - Transmit Interface (TLP TX) + -- ============================================================================================================ + + type t_PCIe_TLP_TX is record + -- Control + valid : std_logic; -- Data valid + ready : std_logic; -- Ready to accept data (backpressure) + sop : std_logic; -- Start of Packet + eop : std_logic; -- End of Packet + + -- TLP Header + header : t_PCIe_TLP_Header; + + -- Payload Data (256-bit for Gen3/Gen4) + data : std_logic_vector(255 downto 0); + keep : std_logic_vector(31 downto 0); -- Byte valid indicators + + -- Error Signaling + err : std_logic; -- Error in TLP + poisoned : std_logic; -- Poisoned TLP + end record; + + -- View from Master (endpoint transmitting TLP) + subtype t_PCIe_TLP_TX_m2s is t_PCIe_TLP_TX; + alias t_PCIe_TLP_TX_Master is t_PCIe_TLP_TX_m2s; + + -- View from Slave (endpoint receiving TLP) + subtype t_PCIe_TLP_TX_s2m is t_PCIe_TLP_TX; + alias t_PCIe_TLP_TX_Slave is t_PCIe_TLP_TX_s2m; + + -- ============================================================================================================ + -- Transaction Layer - Receive Interface (TLP RX) + -- ============================================================================================================ + + type t_PCIe_TLP_RX is record + -- Control + valid : std_logic; + ready : std_logic; + sop : std_logic; + eop : std_logic; + + -- TLP Header + header : t_PCIe_TLP_Header; + + -- Payload Data + data : std_logic_vector(255 downto 0); + keep : std_logic_vector(31 downto 0); + + -- Status + bar_hit : std_logic_vector(6 downto 0); -- Which BAR was hit + err : std_logic; + poisoned : std_logic; + end record; + + subtype t_PCIe_TLP_RX_m2s is t_PCIe_TLP_RX; + alias t_PCIe_TLP_RX_Master is t_PCIe_TLP_RX_m2s; + + subtype t_PCIe_TLP_RX_s2m is t_PCIe_TLP_RX; + alias t_PCIe_TLP_RX_Slave is t_PCIe_TLP_RX_s2m; + + -- ============================================================================================================ + -- Configuration Space Interface + -- ============================================================================================================ + + type t_PCIe_Config is record + -- Device Identification + vendor_id : std_logic_vector(15 downto 0); + device_id : std_logic_vector(15 downto 0); + revision_id : std_logic_vector(7 downto 0); + class_code : std_logic_vector(23 downto 0); + + -- BAR Configuration + bar_enabled : std_logic_vector(5 downto 0); + bar_type : std_logic_vector(5 downto 0); -- 0=32-bit, 1=64-bit + + -- Link Status + link_up : std_logic; + link_width : t_PCIe_LinkWidth; + link_speed : std_logic_vector(3 downto 0); -- Gen1/2/3/4 + + -- Power Management + power_state : t_PCIe_PowerState; + + -- Interrupts + msi_enabled : std_logic; + msix_enabled : std_logic; + max_payload_size: std_logic_vector(2 downto 0); -- 128/256/512/1024/2048/4096 + max_read_req : std_logic_vector(2 downto 0); + end record; + + -- ============================================================================================================ + -- Physical Layer Interface (for reference - typically handled by PHY IP) + -- ============================================================================================================ + + type t_PCIe_Physical_Lane is record + tx_p : std_logic; -- Differential TX positive + tx_n : std_logic; -- Differential TX negative + rx_p : std_logic; -- Differential RX positive + rx_n : std_logic; -- Differential RX negative + end record; + + type t_PCIe_Physical_Lane_Vector is array(natural range <>) of t_PCIe_Physical_Lane; + + -- ============================================================================================================ + -- Helper Functions + -- ============================================================================================================ + + function create_tlp_header( + tlp_type : t_PCIe_TLP_Type; + address : std_logic_vector(63 downto 2); + length : natural; + requester_id: std_logic_vector(15 downto 0); + tag : std_logic_vector(7 downto 0); + be_first : std_logic_vector(3 downto 0) := "1111"; + be_last : std_logic_vector(3 downto 0) := "1111" + ) return t_PCIe_TLP_Header; + +end package; + +package body PCIe is + + function create_tlp_header( + tlp_type : t_PCIe_TLP_Type; + address : std_logic_vector(63 downto 2); + length : natural; + requester_id: std_logic_vector(15 downto 0); + tag : std_logic_vector(7 downto 0); + be_first : std_logic_vector(3 downto 0) := "1111"; + be_last : std_logic_vector(3 downto 0) := "1111" + ) return t_PCIe_TLP_Header is + variable header : t_PCIe_TLP_Header; + begin + -- Set format and type based on TLP type + case tlp_type is + when MRd => + if address(63 downto 32) = x"00000000" then + header.fmt := "00"; -- 3DW header, no data + else + header.fmt := "01"; -- 4DW header, no data + end if; + header.pkt_type := "00000"; + + when MWr => + if address(63 downto 32) = x"00000000" then + header.fmt := "10"; -- 3DW header, with data + else + header.fmt := "11"; -- 4DW header, with data + end if; + header.pkt_type := "00000"; + + when CplD => + header.fmt := "10"; + header.pkt_type := "01010"; + + when others => + header.fmt := "00"; + header.pkt_type := "00000"; + end case; + + header.tc := "000"; -- Traffic Class 0 + header.attr := "000"; + header.th := '0'; + header.td := '0'; + header.ep := '0'; + header.length := std_logic_vector(to_unsigned(length, 10)); + header.requester_id:= requester_id; + header.tag := tag; + header.be_first := be_first; + header.be_last := be_last; + header.address := address; + + return header; + end function; + +end package body; diff --git a/HighSpeed/PCIe/v4/PCIeCommon.vhdl b/HighSpeed/PCIe/v4/PCIeCommon.vhdl new file mode 100644 index 0000000..ce46e9b --- /dev/null +++ b/HighSpeed/PCIe/v4/PCIeCommon.vhdl @@ -0,0 +1,155 @@ +-- ============================================================================= +-- Authors: +-- Parham Soltani +-- +-- Package: +-- Common types, constants, and enums for PCI Express interfaces +-- +-- Description: +-- Following the PCIe 4.0 specification. +-- +-- License: +-- ==================================================================================================================== -- +-- Copyright 2016-2025 Open Source VHDL Group -- +-- -- +-- Licensed under the Apache License, Version 2.0 (the "License"); -- +-- you may not use this file except in compliance with the License. -- +-- You may obtain a copy of the License at -- +-- -- +-- http://www.apache.org/licenses/LICENSE-2.0 -- +-- -- +-- Unless required by applicable law or agreed to in writing, software -- +-- distributed under the License is distributed on an "AS IS" BASIS, -- +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- +-- See the License for the specific language governing permissions and -- +-- limitations under the License. -- +-- ==================================================================================================================== -- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package PCIeCommon is + -- Link speeds + constant PCIE_GEN1_SPEED : natural := 2_500; -- Mbps per lane + constant PCIE_GEN2_SPEED : natural := 5_000; -- Mbps per lane + constant PCIE_GEN3_SPEED : natural := 8_000; -- Mbps per lane + constant PCIE_GEN4_SPEED : natural := 16_000; -- Mbps per lane + + -- Link widths + type t_PCIe_LinkWidth is (x1, x2, x4, x8, x16); + + function to_lanes(width : t_PCIe_LinkWidth) return positive; + + -- TLP Packet Types + type t_PCIe_TLP_Type is ( + MRd, -- Memory Read Request + MRdLk, -- Memory Read Request - Locked + MWr, -- Memory Write Request + IORd, -- I/O Read Request + IOWr, -- I/O Write Request + CfgRd0, -- Configuration Read Type 0 + CfgWr0, -- Configuration Write Type 0 + CfgRd1, -- Configuration Read Type 1 + CfgWr1, -- Configuration Write Type 1 + Msg, -- Message Request + MsgD, -- Message Request with Data + Cpl, -- Completion without Data + CplD, -- Completion with Data + CplLk, -- Completion for Locked Memory Read + CplDLk -- Completion for Locked Memory Read with Data + ); + + -- Transaction Layer Packet Header (32-bit aligned) + type t_PCIe_TLP_Header is record + fmt : std_logic_vector(1 downto 0); -- Format + pkt_type : std_logic_vector(4 downto 0); -- Type + tc : std_logic_vector(2 downto 0); -- Traffic Class + attr : std_logic_vector(2 downto 0); -- Attributes + th : std_logic; -- TLP Processing Hints + td : std_logic; -- TLP Digest Present + ep : std_logic; -- Poisoned Data + length : std_logic_vector(9 downto 0); -- Length in DW + requester_id: std_logic_vector(15 downto 0); -- Bus:Dev:Func + tag : std_logic_vector(7 downto 0); -- Transaction tag + be_last : std_logic_vector(3 downto 0); -- Last DW Byte Enable + be_first : std_logic_vector(3 downto 0); -- First DW Byte Enable + address : std_logic_vector(63 downto 2); -- 64-bit address (DW aligned) + end record; + + -- DLLP (Data Link Layer Packet) Types + type t_PCIe_DLLP_Type is ( + Ack, + Nak, + PM_Enter_L1, + PM_Enter_L23, + PM_Active_State_Request_L1, + PM_Request_Ack, + Vendor_Specific, + NOP, + FC_Init1, + FC_Init2, + FC_Update_P, + FC_Update_NP, + FC_Update_Cpl + ); + + -- Flow Control Credit Types + type t_PCIe_FC_Type is (Posted, NonPosted, Completion); + + -- Flow Control Credits + type t_PCIe_FlowControl is record + fc_type : t_PCIe_FC_Type; + hdr_credits : std_logic_vector(7 downto 0); + data_credits: std_logic_vector(11 downto 0); + end record; + + -- Link Training and Status State Machine (LTSSM) States + type t_PCIe_LTSSM_State is ( + Detect_Quiet, + Detect_Active, + Polling_Active, + Polling_Compliance, + Polling_Configuration, + Configuration_Linkwidth_Start, + Configuration_Linkwidth_Accept, + Configuration_Lanenum_Wait, + Configuration_Lanenum_Accept, + Configuration_Complete, + Configuration_Idle, + Recovery_RcvrLock, + Recovery_RcvrCfg, + Recovery_Idle, + L0, + L0s, + L1_Idle, + L1_Substate, + L2_Idle, + L2_TransmitWake, + Disabled_Idle, + Disabled_LinkWidth_Start, + Loopback_Entry, + Loopback_Active, + Loopback_Exit, + Hot_Reset + ); + + -- Power Management States + type t_PCIe_PowerState is (L0, L0s, L1, L2, L3); + +end package; + +package body PCIeCommon is + + function to_lanes(width : t_PCIe_LinkWidth) return positive is + begin + case width is + when x1 => return 1; + when x2 => return 2; + when x4 => return 4; + when x8 => return 8; + when x16 => return 16; + end case; + end function; + +end package body; diff --git a/build.pro b/build.pro new file mode 100644 index 0000000..34bbd30 --- /dev/null +++ b/build.pro @@ -0,0 +1,58 @@ +# ==================================================================================================================== # +# Copyright 2016-2025 Open Source VHDL Group # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# ==================================================================================================================== # +# VHDLRevision: VHDL-2019 +# VHDLLibrary: Interfaces + +library Interfaces + +# Common definitions +analyze IO/Common.vhdl + +# Internal bus structures +analyze AMBA/AXI/v4/AXI4Common.vhdl +analyze AMBA/AXI/v4/AXI4.vhdl +analyze AMBA/AXI/v4/AXI4_Generic.vhdl + +analyze AMBA/AXI/v4/AXI4Lite.vhdl +analyze AMBA/AXI/v4/AXI4Lite_Generic.vhdl +analyze AMBA/AXI/v4/AXI4Lite.presized.vhdl + +analyze AMBA/AXI/v4/AXI4Stream.vhdl +analyze AMBA/AXI/v4/AXI4Stream_Generic.vhdl + +# Low-speed interfaces +analyze IO/I2C.vhdl +analyze IO/SPI.vhdl +analyze IO/I2S.vhdl +analyze IO/JTAG.vhdl +analyze IO/UART.vhdl + +# Ethernet +analyze IO/Ethernet.vhdl +analyze IO/Cages.vhdl + +# Video interfaces +analyze Video/VGA.vhdl +analyze MIPI/C-PHY.vhdl +analyze MIPI/D-PHY.vhdl +analyze MIPI/M-PHY.vhdl + +# Miscellaneous interfaces +analyze PoC/CSE.vhdl + +# High-speed serial interfaces - PCI Express +analyze HighSpeed/PCIe/v4/PCIeCommon.vhdl +analyze HighSpeed/PCIe/v4/PCIe.vhdl diff --git a/compileorder.list b/compileorder.list index afa443d..73ad8f1 100644 --- a/compileorder.list +++ b/compileorder.list @@ -50,3 +50,7 @@ MIPI/M-PHY.vhdl # Miscellaneous interfaces PoC/CSE.vhdl + +# High-speed serial interfaces - PCI Express +HighSpeed/PCIe/v4/PCIeCommon.vhdl +HighSpeed/PCIe/v4/PCIe.vhdl